JPS631165A - Vertical driving generation circuit - Google Patents

Abstract

PURPOSE:To eliminate the effect of the pulse width on a vertical synchronization output by comparing the phase of a reset pulse of a frequency division circuit with that of an output pulse of a frequency division circuit in response to a vertical synchronization separation output signal so as to discriminate the period of a vertical synchronizing signal. CONSTITUTION:The vertical synchronizing signal from a vertical synchronization separation circuit 9 is fed to a reset pulse generating circuit 14 via an input selection circuit 13, a reset pulse is fed to a vertical count-down circuit 11 and a vertical drive pulse is generated at an output terminal 20. If a prescribed time elapses, the 2nd frequency division output signal, phi2 is generated, a reset pulse in response to the next vertical synchronizing signal is venerated from the circuit 14 also, and when a television signal is inputted to a terminal 10, the phases of two signals coincide, and an output signal of a phase comarator circult 19 is inverted to an H level via a signal selection circuit 18. Thus, the signal,phi2 is fed to the circuit 14 via the input selection circuit 13 and the circuit 11 generates a vertical drive pulse with a prescribed period at an output terminal 20 while not being affected by an external vertical signal.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Industrial Application Field The present invention relates to a countdown type vertical drive pulse generation circuit used in television receivers, etc.
In particular, the present invention relates to a vertical drive pulse generation circuit that can determine whether a vertical synchronization signal included in a received signal is correct or not, and can generate correct vertical drive pulses.

(b) Conventional technology A countdown type vertical drive pulse generation circuit is described in Japanese Patent Publication No. 7786/1986. Figure 2 shows the circuit, in which a clock signal with twice the frequency of the horizontal synchronizing signal supplied to terminal (1) is divided by 11525 by frequency divider (2) and has a predetermined pulse width. A frequency-divided output signal is generated at terminal (3). Further, the composite synchronization signal input to the terminal (4) is synchronized and separated by the vertical synchronization separation circuit (5). The Nant gate (6) compares the phases of the output signal of the vertical synchronization separation circuit 5) and the divided output signal of the frequency divider (2), and when the phases match, the octal counter (7)
Reset. When the octal counter 7) is reset, its output is used to set the reset signal selection circuit (8) to the side that receives the divided output signal of the frequency divider (2).

Therefore, the frequency divider (2) performs accurate 11525 frequency division operation without depending on an external vertical synchronization signal. Furthermore, if the frequency-divided output signal of the frequency divider (2) and the vertical synchronization signal are not synchronized, the octal counter (7) counts the vertical synchronization signal without being reset by the Nant gate (6). ,
After counting eight times, the output of the octal counter (7) is used to set the reset signal selection circuit (8) to the side that receives the output signal of the vertical synchronization separation circuit (5). For this reason, the frequency divider (
2) performs frequency division operation according to the vertical synchronization signal.

Therefore, according to the circuit shown in FIG. 2, even when the frequency divided output signal of the frequency divider (2) and the vertical synchronization signal are in an asynchronous state, the vertical synchronization signal is counted eight times by the octal counter (7), and the vertical synchronization signal is counted eight times. With the second vertical synchronization signal, the frequency-divided output signal of the frequency divider (2) and the vertical synchronization signal can be synchronized.

(C) Problems to be Solved by the Invention However, in the circuit shown in Figure 2, a video signal that does not have the normal vertical period of 262.5H (H is one period of the horizontal synchronizing signal) from the broadcasting station at the terminal (4) There is a problem in that synchronization is disrupted when the vertical synchronization signal from a tape recorder, personal computer, etc. is not applied. For example, 262
When a vertical synchronizing signal with an H period and a pulse width of 3H is fully applied to the terminal (4), in the phase comparison by the Nant gate (6), since the pulse width of the vertical synchronizing signal is as long as 3H,
The phases are judged to match. Then, the octal power counter 7) is reset, and the frequency divider (2
) will now be reset every 262.5H,
The playback screen shifts little by little.

Eventually, the phases of the signals applied to the Nant gate (6) no longer match, and when the octal counter (7) counts the vertical synchronization signal eight times, the frequency divider (2) is reset according to the vertical synchronization signal. It becomes like this. Then, the Nandt gate (6) again judges that the phases match. For this reason, the Nantes gate (6) repeatedly judges whether or not the phases match, causing the problem that the playback screen moves up and down.

(d) Means for Solving the Problems The present invention has been made in view of the above points, and includes a vertical synchronization separation circuit that synchronously separates a composite synchronization signal to generate a vertical synchronization signal, and a horizontal synchronization signal. a vertical countdown circuit that receives a clock signal of N times the frequency and divides the frequency of the clock signal to generate a pseudo vertical synchronization signal; a selection circuit that switches and outputs the two vertical synchronization signals; and an output of the selection circuit. a reset pulse generation circuit that generates a reset pulse for the vertical countdown circuit in response to a signal; and a phase comparison between a frequency-divided output signal of the vertical countdown circuit and the reset pulse, and switches the selection circuit in accordance with the phase difference. It is characterized by having a phase comparison circuit.

(*) Effect According to the present invention, a phase comparator compares the reset pulse applied to the frequency dividing circuit according to the vertical synchronization separation output signal and the pulse of a predetermined period generated from within the frequency dividing circuit. ,
Since the period of the vertical synchronization signal is determined, it is not affected by the pulse width of the vertical synchronization separation output.

(F) Embodiment FIG. 1 is a circuit diagram showing an embodiment of the present invention, in which (9) synchronously separates a composite synchronous signal input to the terminal (10),
A vertical synchronization separation circuit (11) extracts the vertical synchronization signal, and counts the clocks of 2f' and (r is the frequency of the horizontal synchronization signal) applied to the terminal (12) to extract the first to fifth signals.
A vertical countdown circuit that generates output numbers (φ1 to φ6); (13) an input selection circuit that switches between the vertical synchronization signal from the vertical synchronization separation circuit (9) and the second output signal 4°; <14 ) is a reset pulse generation circuit that generates a reset pulse of a predetermined pulse width according to the output signal of the input selection circuit (13), (15) is a second output signal, and
(16) is a gate circuit that allows the vertical synchronization signal to pass according to the fourth output signal φ; (17)
represents the output signal of the gate circuit (16) as the third output signal φ
A holding circuit (18) holds the output signals of the reset pulse generation circuit (14) and the delay circuit (15) until , is applied, or the output signal of the holding circuit (17) and the first output signal φ1. A signal selection circuit (19) compares the phases of the two outputs of the signal selection circuit (18), and switches the input selection circuit (13) and the signal selection circuit (18) based on the output signal. This is a phase comparator circuit to control.

The vertical countdown circuit (11) has 10 stages of T-F.
It consists of an F (FF: flip-flop circuit) and a decoder, and uses the 2fH signal supplied from the terminal (12) as a clock to divide the frequency by the 10 stages of T-FF, and decodes the divided output of each. The first output signal φ is a signal that becomes "rH" level from the time the beam is set until 4H, the second output signal φ is a signal that becomes "H" level after 261.5H, and the third output The signal φ is at “H” level from 8H to 17H, and the fourth output signal φ4
is r H between 261H and 1.5H, the signal that becomes the level and the fifth output signal φ, and r H between 8H from the beam set
This is a signal that generates a J-level vertical drive pulse at the output terminal (20).

In the case of the NTSC system, the period of the vertical synchronization signal from the broadcasting station is 262.5H. On the other hand, the period of the vertical synchronizing signal from an external device other than the broadcasting station, such as a video tape recorder or a personal computer, fluctuates due to various causes. Therefore, in this specification, a signal including a vertical synchronizing signal with a period of 262.5H is referred to as a television signal, and a signal including a vertical synchronizing signal with a period other than 262.5H is referred to as a video signal.

Next, the operation will be explained. For example, in the circuit shown in FIG. 1, assuming that the phase comparator circuit (19) generates an output signal of level r L
), the input selection circuit (13) selects and outputs the vertical synchronization signal of the vertical synchronization separation circuit (9), and the signal selection circuit (18) selects and outputs the vertical synchronization signal from the delay circuit (15) and generates a reset pulse. The signal from the circuit (14) is selectively output. In this state, when the video signal is input from the terminal (10) to the vertical sync separation circuit (9), the vertical sync signal that has been sync-separated is sent to the input selection circuit (14). 13) to the reset pulse generation circuit (14).Therefore, a reset pulse having a predetermined pulse width according to the vertical synchronization signal is applied to the reset terminal of the vertical countdown circuit (11), and the reset pulse is applied to the reset terminal of the vertical countdown circuit (11). A vertical drive pulse corresponding to the reset pulse is generated at the output terminal (20). After a predetermined time has elapsed after the vertical countdown circuit (11) is reset, a second output signal φ is generated, and this signal is transmitted to the delay circuit. (
15) to the signal selection circuit (18).

Then, a reset pulse corresponding to the next vertical synchronization signal is also generated from the reset pulse generation circuit (14) and applied to the signal selection circuit (18). In that case, the signal selection circuit (
18) is switched as described above by the control signal from the phase comparator circuit (19), so the two signals pass through as is.

Now, if the input signal that can be applied to terminal 0) is a video signal, the phases of the two signals will not match, and the output signal of the phase comparison circuit (19) will remain at the "L" level and will not change.

Next, if the input signal applied to the terminal (10) is a television signal, the phases of both signals match and the phase comparator circuit (19)
) is inverted to "H" level.

Therefore, the input selection circuit (13) is in a state of selectively outputting the second output signal φ2, and the signal selection circuit (18) is switched to take in the holding circuit (17) and the first output signal φ1.

As a result, the second output signal φ is applied to the reset pulse generation circuit (14), so the vertical countdown circuit (11) performs a self-resetting operation and is not affected by the external vertical synchronization signal. First, -periodical vertical drive pulses are generated at the output terminal (20.).

By the way, the fourth output signal φ4 of the vertical synchronization signal from the vertical synchronization separation circuit (9) is a control signal (so-called window signal).
The signal is applied to the holding circuit (17) through the gate circuit (16). The holding circuit (17) becomes rH when the vertical synchronizing signal is applied.

The rH'' level signal is applied together with the first output signal φ1 to the phase comparator circuit (19) via the signal selection circuit (18). At this time, since the vertical synchronization signal of the television signal has arrived from the vertical synchronization separation circuit (9), the phases of the two signals in the phase comparison circuit (9) match, and the output can be maintained. It will remain as it is.

If switching to an external device or another channel is performed in this state, the phase relationship between the synchronized vertical synchronization signal and the fourth output signal φ4 generated by the vertical countdown circuit (11) will be disrupted, and the vertical The synchronization signal is a gate circuit (16
) cannot pass through. Furthermore, when the electric field is weak, the vertical synchronization signal is lost. In that state, the holding port 18 (1
The output of 7) becomes rL'' level in response to the third output signal φ, and the signal selection circuit (18>) applies the rL'' level signal and the first output signal φ to the phase circuit (19).

At this time, the phases of both signals in the phase comparison circuit (19) become inconsistent, and the output is again inverted to "L" level. As a result, the vertical countdown circuit (11) comes to be reset by the vertical synchronization signal arriving from the outside, and a vertical drive pulse synchronized with it can be obtained at the output terminal (20).

Therefore, according to the circuit shown in FIG. 1, when a video signal has arrived, the vertical countdown circuit (11) is reset in accordance with the vertical synchronization signal in the video signal, and the corresponding vertical drive pulse is generated. When a television signal arrives, the vertical countdown circuit (11) is reset in accordance with the frequency-divided output signal of the vertical countdown circuit (11), and a corresponding vertical drive pulse is generated. You will be able to get it.

FIG. 3 is a circuit diagram showing a specific example of the circuit shown in FIG.
) indicates an input selection circuit, (22) a D-FF indicating a reset pulse generation circuit, (23) a signal selection circuit, and (deaf) a phase comparison circuit.

In Figure 3, the 5-RFP (2
Assuming that the Q output of 5) is at the "L" level and the Q output is at the "H" level, the 6 outputs are the AND gate (26).
, (27) and (28), and the Q output is applied to the AND gates (29), (30) and (31).
) can be applied. In this state, the vertical synchronization separation circuit (32
) when the vertical synchronizing signal shown in FIG. At the timing of , a signal of level rH is applied to the OR gate (33). or gate (3
3), the seventh output signal that changes from 296H to rH level is applied, so the rH level signal is applied to the D input of the D-FF (22) at the rising timing. The signal 2r, 4 shown in Fig. 4 (a) has been applied to the C (clock) terminal of the D-FF (22).
Since D-FF (22) performs a falling operation, 261
．． At the falling edge of 5H, the rH'' level signal is transferred to the Q output. Therefore, the vertical countdown circuit (34) is reset in accordance with the Q output, and the sixth
The output signal -6 has a level of r L and is passed through the AND gate (28) and the OR gate (33) to the D-FF (2
2) is applied to the C terminal. Therefore, at the next falling edge of the clock of 2f'H, that is, 262H, r L ''
Since the level signal is transferred to the Q output, a signal with a pulse width of 0.5H as shown in FIG. 4(c) is generated as a reset pulse. The reset signal is 21H in Figure 4 (a).
It is applied to the Nant gate (35) along with the clock pulse, and the pulse shown in FIG. The voltage can be applied to the C terminal.

On the other hand, the vertical countdown circuit (34) outputs 261.
The second output signal φ as shown in FIG. 4 (N) rises at 5H,
is applied to the C terminal of the D-FF (38), and is delayed by 0.5H by the 2f14 clock pulse, as shown in Fig. 4 (to).
A signal with a pulse width of 0.5H such as
) and the OR gate (39) to the C terminal of the D-FF (37). Therefore, C of D-FF (37)
At the falling timing of the signal shown in Fig. 4 (d) when the signal is applied to the terminal C, r in Fig. 4 (f) is applied to the C terminal.
The "L" level signal can be transferred to the Q output. For this reason, D
-Q output of FF (37) is "L" level, Q output is r
The third output signal φ becomes H level and the AND gate (
40) to the octal counter (41), and when it has counted eight times, the octal counter (41)
Reset P (25) and hex counter (42). Therefore, S-RF F(25)(7)Q output 4t
'L' L, HEL, Q output maintains rH, level state. As a result, the vertical countdown circuit <34
) generates a vertical drive pulse at the output terminal (43) in response to the vertical synchronization signal of the video signal.

Next, when the vertical synchronization signal of the television signal whose rising edge is between 261.5H and 262H as shown in FIG. The vertical synchronization signal is sent to the D-FF (
22) can be applied to the D terminal. For this reason, D-FF (22
) At the falling edge of 262H of the clock signal in Figure 5 (a) which has been applied to the C terminal of
After being transferred to the output, the vertical countdown circuit (34) is reset, and its reset pulse becomes as shown in FIG. 5(c). Therefore, a signal as shown in Figure 5 (2) is generated from the Nant gate (35) and applied to the C terminal of the D-FF (37) via the AND gate (27) and the NOR gate (36).

- On the other hand, as in the case described above, the second output signal φ shown in FIG.
The Q output becomes as shown in Fig. 5 (to), and the AND gate (
26) and D-FF (37) via Noah Gate (39)
) can be applied to the D terminal. Therefore, D-FF(37)
At the falling timing of the signal shown in Fig. 5 (d) which is applied to the C terminal of the
The 1H'' level signal of Therefore, the Q output of the D-FF (37) becomes the "H" level, the d output becomes the rLJ level, and the third output signal ≠ is sent to the hexadecimal counter (42) via the ant game (44).
When the application is completed and 16 times are counted, the hexadecimal counter (42) sets S-RF P (25) and resets the octal counter (41).

Therefore, the Q output of S-RF P (25) becomes "H" level and the d output becomes "L" level, and their states are inverted. As a result, the second output signal φ, becomes the AND gate (28
) and or game h (33), D-FF (22)
Also, the voltage is applied to the D terminal of the NOR gate (39
), the Q output of 5-RFP (45) is connected to the AND gate (2
9), and the first output signal 4I can be applied to the NOR gate (36) via the AND gate (30). Since the second output signal φ is applied to the D terminal of the D-FF (22), the vertical countdown circuit (3
4) is the output terminal (
43) occurs.

- On the other hand, in this state, the vertical synchronization separation circuit (32) receives the signal from the vertical synchronization separation circuit (32).

As shown in Figure 6 (b), the rise is from 261.5H to 2
When a vertical synchronizing signal slightly shifted from the interval 62H arrives, it is gated by the fourth output signal φ4 in FIG.
5) The set human power S can be applied completely. Therefore, S-R
The Q output of F Fe12) is as shown in Fig. 6 (d), and is connected to D via the AND gate (29) and OR gate (39).
- Applied to the D input of FF (37). Further, the vertical countdown circuit (34) is reset by a reset pulse corresponding to the second output signal φ as shown in FIG. 6(E).
The first output signal φ, as shown in FIG. shall be. Since the Q output is already at the "H" level due to the above operation, its state does not change and the S-R
F P (25) continues to receive television signals. Note that S-RF F (45) can be reset at 8H due to the third output signal≠.

In this state, when switching to an external device or another channel is performed and a vertical synchronization signal with a long period and a disordered phase as shown in FIG. 6(g) is generated from the vertical synchronization separation circuit (32), the vertical The synchronizing signal cannot pass through the AND gate (46), and the Q output of the 5-RFF (45) becomes l″L″ level. Therefore, the D terminal of D-FF (37) is always rL
'' level, and since the first output signal φ1 is applied to the C terminal, a signal of level r L is generated at the Q output at the fall of 4H. Therefore, the third output signal φ is passed through the AND gate (40) to the octal counter <4
1) is applied, and when the count is completed 8 times, S-RF
P (25) and hex counter (42) are reset. Therefore, the Q output of S-RF F (25) becomes rL'' level and the σ output becomes 1H'' level so as to again take in the external vertical synchronization signal.

In addition, hexadecimal counter (42) and octal counter (41)
The third output signal φ from the AND gates (44) and (40) is counted 16 times and 8 times, respectively, and then an output signal of a predetermined pulse width is generated, and the counting operation is always performed. Moreover, the seventh output signal φ is S −R
When the ◇output of F F (25) selects the vertical synchronization signal that arrives at the "H" level, and the vertical synchronization signal does not arrive, the vertical countdown circuit (34) is set to 297.
This is a signal for resetting at H cycle.

(g) Effects of the Invention As described above, according to the present invention, in order to discriminate between a television signal and a video signal, the reset pulse of the vertical countdown circuit and the frequency-divided output of the vertical countdown circuit are compared in phase. Therefore, the vertical drive pulse can be stably obtained without being affected by the pulse width of the incoming vertical synchronization signal, and there is no problem that the playback screen will flow even when receiving signals from external equipment.

In addition, as in the embodiment, this is determined by phase comparison, and after determining that a television signal is being received, the vertical countdown circuit is activated (self-reset), and the vertical synchronization signal that arrives from the outside is activated. Since a window is provided and it is determined whether or not the vertical synchronization signal exists within the window, the sensitivity of the determination can be changed and abnormal switching can be prevented.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing one embodiment of the present invention. (9)...Vertical synchronization separation circuit, (11>...Vertical countdown circuit, (13)...Input selection circuit,
(14)...Reset pulse generation circuit, (15
)...Delay circuit, (18)...Signal selection circuit, (1
9)...Phase comparison circuit. Applicant Sanyo i-ki Co., Ltd. and one other agent Patent attorney Takuji Nishino and one other person Figure 2. Figure 4 A2H utrHiuz, rt-t ----Figure 5 (f)

Claims (1)

[Claims] (1) A vertical synchronization separation circuit that synchronously separates a composite synchronization signal to generate a vertical synchronization signal, and a vertical synchronization separation circuit that receives a clock signal with a frequency N times that of the horizontal synchronization signal, divides the frequency of the clock signal, and generates a pseudo vertical synchronization signal. a vertical countdown circuit that generates a vertical countdown; a selection circuit that switches and outputs the two vertical synchronization signals;
a reset pulse generation circuit that generates a reset pulse for the vertical countdown circuit in response to an output signal of the selection circuit, and a phase difference between the frequency-divided output signal of the vertical countdown circuit and the reset pulse; and a phase comparison circuit that switches the selection circuit, and resets the vertical countdown circuit in response to the vertical synchronization signal or the pseudo vertical synchronization signal to generate a vertical drive pulse. Vertical drive pulse generation circuit.