JPS63227228A - Detector for modem training signal - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Summary] A detection circuit for a modem training signal as a switching signal when switching the encoding mode of an ADPCM encoder depending on whether the input signal is a voice signal or data modulated by a modem, In addition to the circuit that synchronously detects the carrier of the modem signal using a PLL loop, the signal power of the modem signal's upper limit frequency, the signal power of the carrier frequency, and the signal power obtained by removing the upper limit frequency, carrier frequency, and lower limit frequency components from the input signal. This eliminates false detection of training signals by providing a circuit to determine the power of each power and determining the ratio of each power to the total signal input power.

[Industrial application field]

The present invention provides adaptive differential PCM coding (AD) of voice-band signals.
PCM) transmission method, especially modem training (No. 8 detection circuit The modem in question is a 9600 bit/s modem according to CCITT Recommendation v.29, which is standardized for leased lines.

Audio Signals and CCITT Recommendation v, 29, 9600 bi
The data modulated by the t/s modem is converted to ADPCM on the transmitting side.
When encoding, since the spectral properties of both signals are different, the encoder switches to the optimal encoding mode for each signal, encodes it, and transmits it.

When decoding a received signal on the receiving side, the decoding mode of the decoder must be switched to match the encoding mode on the transmitting side, but on the receiving side, the received signal is first modulated by an audio signal or a modem. Data must be identified.

Since it is difficult to identify whether a received signal is data modulated by a modem, it is possible to detect a test signal for initial setting of the modem, that is, a modem training signal, and identify the type of received signal from the detected signal. It is being done.

A modem training signal detector detects the presence or absence of a modem training signal from a received signal and identifies whether the received signal is a data modem signal or a voice signal. It is hoped that false detections will not occur due to such factors.

[Conventional technology]

FIG. 4 is a block diagram of a conventional modem training signal detector, and FIG. 3 is an explanatory diagram for explaining its operation.

This modem training signal detector circuit is
This is because the 9600 bps modem specified in T Recommendation V, 29 D has the main specifications shown in Figure 3A, the eye diagram shown in B, and the synchronization signal shown in C before transmitting data. , the modem's initial setting training signal is composed of the A-8 pattern (alternating pattern), which is a simple repetition of the A vector and B vector of B in the same figure, with a lower limit frequency of 500 Hz and a carrier frequency of 170 Hz.
By focusing on the fact that the signal structure is such that a composite sine wave with components of 0 Hz and an upper limit frequency of 2900 Hz is repeated at regular intervals, it is possible to determine whether the input signal is a data modem signal by detecting the modem training signal. This is to identify that the signal is not an audio signal.

The circuit shown in Fig. 4 includes a bandpass filter 1 that extracts a signal near the specified carrier frequency 1700H2 of the modem signal from an input signal, and a signal having a carrier frequency near 1700Hz that has passed through the bandpass filter 1. A phase-locked loop (PLL) 2 is provided, and a multiplier 31 multiplies the real part cos(θ.+ω)t of the output of the PLL by the signal cosθ′t passed through the band-pass filter 1 to perform synchronous detection; A low-pass filter 32 removes harmonics from the detected output to produce only a DC output, and a zero-crossing discriminator 33 identifies that the sign of the DC output does not change for a certain period of time, and outputs a detection signal Ec.

The input signal is also input to a 2900Hz band filter 51, which converts the input signal to the modem signal's upper limit frequency of 2900Hz.
290011z extracted power A1 is obtained by extracting the component and integrating the extracted output with the root mean square integrator 52. Also,
The entire input signal is integrated by the root mean square integrator 41 to obtain the entire input signal power C1, and the power C1 is given a coefficient γ (where O<
A value γC1 multiplied by γ<1) is output.

The above 2900Hz extracted power A1 and the total input signal power C
γC1, which is 1 multiplied by the coefficient γ, is compared in comparator 7, and 29
When it is detected that the 00Hz extracted power AI is a certain percentage of the total input signal power C1 of 1 or more, a detection signal Ecl is output.

A conventional modem training signal detector outputs a modem training signal detection signal C to the outside when two detection signals, the detection signal Ec and the detection signal Ecl, are simultaneously output for a certain period of time.

The detection signal C of the modem training signal detector identifies that the input signal is a data modem signal, and is therefore used to switch the encoding mode of the ADPCM encoder as described above.

The conventional modem training signal detector shown in FIG.
134638 and Japanese Patent Application No. 60-180181.

[Problem that the invention seeks to solve]

As described above, the conventional modem training signal detector shown in FIG. 4 is a circuit that detects the change in the DC component of the synchronous detection output of the signal near the modem carrier frequency of 1700 Hz extracted from the input signal to obtain the detection signal Ec. , consists only of a circuit that detects the ratio γ of the component near the upper limit frequency 2900H2 of the modem signal to the total power and obtains the detection signal Ecl, so for example, following a single sine wave of frequency 1700Hz, In cases such as when a single sine wave is input, or when a sine wave with a frequency of 170011z is input following a single sine wave with an inverse frequency of 2900Hz, even though no training signal is actually input. First, the detection signal EC of the synchronous detection output for the 1700Hz component and the comparison detection signal Eel of the 2900Hz component are both output in the same way as when the modem training signal is input, so there is no problem of false detection. be.

[Means for solving problems]

In addition to the conventional circuit shown in Figure 4, this problem is caused by the input signal, the modem signal's upper limit frequency (2900Hz), carrier frequency (1700Hz), and lower limit frequency (500Hz).
Upper, middle and lower frequency removal output means 6 is provided to obtain signal power B1 with signal components in the vicinity of The power AI in the upper limit frequency (2900H2) band is equal to or less than a predetermined ratio β of the power A1 in the upper limit frequency (2900Hz) band, that is, βA1, and the power AI in the upper limit frequency (2900H2) band is equal to or higher than a predetermined ratio γ of the total power CI of the input signal, that is, 101 or more. This problem is solved by the circuit configuration of the present invention in which comparators 8 and 9 are provided to detect the training signal.

In the principle block diagram of FIG. 1 showing the configuration of the present invention, 1 indicates the modem signal carrier frequency (17
2 is a phase-locked loop (PLL circuit) that can synchronize with a signal near the carrier frequency (17000, z) extracted by the carrier signal extraction means 1; 3 is a A synchronous detection detection circuit that synchronously detects the signal extracted by the carrier signal extraction means 1 using the output of the phase-locked loop 2 and detects that the DC component of the detection output remains unchanged over a certain period of time; 4 squares the total frequency of the input signal; A total power output means for outputting the total power of the input signal on average; 5 is an upper limit frequency output means for extracting the upper limit frequency (2900 Hz) component of the modem signal from the input signal; 6 is an upper limit frequency output means for extracting the upper limit frequency (2900 Hz) component of the modem signal from the input signal; Frequency (2900Hz), carrier frequency (1
700Hz), upper, middle and lower frequency removal output means for outputting signal power from which signal components in the vicinity of the lower limit frequency (500Hz) have been removed; 7 compares the output of the total power output means 4 and the output of the upper limit frequency output means 5; A first comparator 8 compares the output of the upper limit frequency output means 5 with the output of the upper middle and lower frequency removal output means 6; 9 predetermines the output of the upper middle and lower frequency removal output means 6; A third comparator 10 that compares the output of the synchronous detection detection circuit 3, the output of the first comparator 7, the output of the second comparator 8, and the output of the third comparator 9 is kept constant at the same time. It is a determination output means that outputs a signal C when the time is output.

[Effect]

The carrier signal extraction means 1 of the modem training signal detector of the present invention extracts a signal component near a prescribed carrier frequency (170 (182)) of a modem signal from an input signal,
The phase-locked loop 2 operates as a PLL circuit that can be pulled into a signal near the carrier frequency (1700 Hz) extracted by the carrier signal extraction means 1. The synchronous detection detection circuit 3 multiplies the output of the phase-locked loop 2 by the carrier frequency component of the modem signal extracted by the carrier signal extraction means 1 to perform synchronous transverse waveforming, and determines whether the sign of the DC component of the detection output remains unchanged for a certain period of time. It detects and outputs a detection signal Pc.

The total power output means 4 is a DC signal equivalent to the total power of the input signal obtained by averaging the squares of signals of all frequencies of the input signal.

is calculated, the value is multiplied by a predetermined ratio γ, and the result is output.

The upper limit frequency output means 5 extracts and detects the upper limit frequency (29008Z) component of the modem signal from the input signal, and outputs the corresponding DC signal A1 and the value A1 multiplied by a predetermined ratio β.

Upper, middle and lower frequency removal output means 6 extracts from the input signal the upper limit frequency (2900 Hz) of the modem signal and the carrier frequency (
1700 Hz), outputs a DC signal B1 corresponding to signal power excluding components near the lower limit frequency (500 Hz).

The first comparator 7 outputs a detection signal Ecl when the output A1 of the upper limit frequency output means 5 is equal to or higher than the output γci of the total power output means 4.
Output.

The second comparator 8 outputs the output 8 of the upper, middle and lower frequency removal output means 6.
1 is less than the output βAl of the upper limit frequency output means 5, the detection signal Ec2 is output.

The third comparator 9 outputs the output B of the upper, middle and lower frequency removal output means 6.
1 is less than a predetermined threshold value α, a detection signal Ec3 is output.

The determination output means 10 outputs the output Ec of the synchronous detection detection circuit 3, the output Ecl of the first comparator 7, and the output Ec2 of the second comparator 8.
and the output Ec3 of the third comparator 9 are simultaneously output for a certain period of time, a detection signal C is output.

The modem training signal detector of the present invention uses the detection signal Ec output from the synchronous detection detection circuit 3 and the first comparator 7.
When four detection signals, namely the detection signal Eel output from the , the detection signal Ec2 output from the second comparator 8, and the detection signal Ec3 output from the third comparator 9, are output simultaneously for a certain period of time, training is performed. Detects the signal and outputs a detection output C.

Here, ■The reason for comparing the total power of the input signal and the upper limit frequency component, ■The reason for comparing the upper limit frequency component and the output of the upper middle and lower frequency removal output means, ■The output of the upper middle and lower frequency removal output means and the threshold value α Explain the reason for comparing.

The reason for the first part is that when receiving the AB pattern, the received frequency components are 500Hz, 1700) fz, 290
0)1z, so the upper limit frequency component (2900
Hz) is a constant ratio to the total power of the received frequency, this is to detect whether or not this state is present.

If the input signal is not a training signal, the total power component will be extremely larger than the upper frequency component. However, this method alone has the drawbacks described in the prior art.

Next, the reason for (2) is that while the AB pattern is being received, the received frequency components are fixed, so the level of the output from the upper, middle, and lower frequency removal output means is extremely low, except for those based on noise. On the other hand, since the upper limit frequency component is large, this is to detect whether this state is present or not. In the case of an audio signal or a modem signal, the output from the upper, middle and lower frequency removal output means becomes extremely large.

The reason for the last item (■) is that while the AH pattern is being received, the received frequency component is fixed, so the output from the upper, middle, and lower frequency removal output means is extremely small, and in other cases it is large.

Here two single sine waves 1700Hz, 2900Hz
Consider the case where the following are input sequentially in chronological order.

First, when a 1700Hz signal is received and then a 290011z signal, the output from the upper, middle and lower frequency removal output means 6 is extremely small, and the third comparator 9 outputs a detection signal E.
c3 is output, but when the output of the upper limit frequency output means 5 and the output of the upper middle and lower frequency removal output means 6 are compared, it is 170.
While receiving the 0Hz signal, the upper limit frequency output means 5
Since the output level of is low, the second comparator 8 does not output the detection signal Ec2, and the input signal total voltage output means 4
The detection signal Ec1 is not outputted from the first comparator 7 either, and therefore the detection output C is not obtained from the determination output means 10.

Also, first receive a 2900Hz signal, then 1700Hz
The same applies when a signal is received.

On the other hand, while receiving the AB pattern, since the detection signals Bc 1 , Ec2 and Ec3 are obtained from the first, second and third comparators, respectively, the detection signal is obtained from the determination output means 10.

Therefore, the single sine wave 17001 (
When a single sine wave 2900 II z signal is input following the z signal, and vice versa, it is not possible to satisfy all of the above four conditions at the same time, so even if there is no training signal input, Regardless, if it is present, false detection will no longer occur and the problem will be solved.

〔Example〕

FIG. 2 is a block diagram showing the configuration of a modem training (No. 8 detector) according to an embodiment of the present invention.

This example uses 9600 bps of CCITT Recommendation v, 29.
An example of a modem training signal detector for distinguishing from voice signals when transmitting data using a modem,
The modem signal carrier signal extraction means 1 extracts from the input signal a specified carrier frequency of 1700H for the 9600 bps modem.
Bandpass filter 1700Hz that extracts signal components near z
It is BPF.

Phase locked loop 2 is a bandpass filter 1700Hz BPF
A delay device 22 that delays the output signal cosθt by 1 bit, a multiplier 23 that adds a carrier offset ω to the output of the delay device 22, a multiplier 24 that adds a fixed phase ejθ0 to the output of the multiplier 23, and a multiplier 24 that adds a fixed phase ejθ0 to the output of the multiplier 23. The imaginary part si of the output of 24
n (θ, +ω)t in the bandpass filter 1700
A multiplier 21 that multiplies the output signal cosθ′t of the HzBPF.
, a polarity discriminator 25 that sends out 1 or -1 depending on the positive or negative polarity of the output of the multiplier 21, a multiplier 26 that multiplies the output of the polarity discriminator 25 by a coefficient δ, and the output of the multiplier 26 and the previous bit. an adder 27 that adds the outputs of the adder 27; a limiter 28 that adaptively controls the output of the adder 27 to limit the carrier offset ωΦ value; It consists of a delay device 29.

The synchronous detection detection circuit 3 includes the carrier signal extraction means 1 17
00Hz BPF extraction output cos θ′ is the real part of the output ej (θ, +ω) of the phase-locked loop 2, that is, the multiplier 2
A multiplier 31 that multiplies the output signals coscO, +ω)t of 4.
, a low-pass filter 32 that extracts the DC component from the output of the multiplier 31 by removing harmonics, and a zero-crossing discriminator 33 that identifies zero-crossings in the DC output of the low-pass filter 32 and identifies changes in positive and negative signs. Become.

The input signal total power output means 4 includes an integrator 41 that integrates the root mean square of all frequency components of the input signal;
This circuit is composed of a multiplier 42 that multiplies the output C1 of 1 by a coefficient γ smaller than 1, and outputs a DC output γC1.

The upper limit frequency output means 5 includes a band pass filter 2900H2BPP 51 that extracts the upper limit frequency 2900 Hz component of the modem signal from the input signal, an integrator 52 that takes the root mean square of the output, and a DC output A1 of the integrator 52. 2900Hz consisting of a multiplier 53 that multiplies by a smaller coefficient β
This is an extraction circuit and outputs a DC output A1 and a DC output βA1.

Upper, middle and lower frequency removal output means 6 extracts a component of the upper limit frequency of 2900 Hz of the modem signal and carrier frequency 1 from the input signal.
700) Consists of a band-rejection filter 61 that removes fz components and components of a lower limit frequency of 500 Hz, and an integrator 62 that integrates the root mean square of its output, and outputs a DC output Bl.

The first comparator 7 outputs a detection signal Ec when the output AI of the upper limit frequency output means 502 and the root mean integrator 52 is a predetermined ratio 1 or more of the output C1 of the integrator 41 of the total power output means 4.
Output l.

The second comparator 8 outputs a detection signal E when the output B1 of the integrator 62 of the upper middle and lower frequency removal output means 6 is less than a predetermined ratio β of the output AI of the integrator 52 of the upper limit frequency output means 5.
Output c2.

The third comparator 9 outputs a detection signal Ec3 when the output B1 of the integrator 62 of the upper, middle and lower frequency removal output means 6 is equal to or less than a predetermined threshold value α.

The judgment output means 10 includes an AND circuit 101 and a counter 10
The AND circuit 101 consists of the output Ec of the synchronous detection detection circuit 3, the output Ecl of the first comparator 7, and the second comparator 8.
When the output εc2 of
When it is confirmed that this continues for a certain period of time, a detection signal C is output.

The modem training signal detector of this embodiment has a detection output Ec that is output by detecting that the sign of the synchronous detection output of the carrier signal extracted from the input signal remains unchanged for a certain period of time;
The relationship among the output γC1 of the input signal total power output means 4, the outputs A1 and βA1 of the upper peak frequency output means 5, and the output B1 of the peak frequency removal output means 6 is as follows: ■ Bl(α, (α: threshold) ■ Bl(βA1.(0”Cβ<i>■ AI
)rcl, (0<γku1) ■, ■, ■ Since the mode t training signal is detected by simultaneously satisfying all of
If 11z is followed by 290011z, and vice versa, the above condition ■ is satisfied, but ■,
Since the condition (2) cannot be satisfied, there is no problem because it will not be erroneously detected that there is a training signal input even though there is no input.

〔Effect of the invention〕

As explained above (according to the present invention), a single sine wave 1700 equal to the carrier frequency of the modem signal is used as the human input signal.
Hz followed by 290 equal to the upper limit frequency of the modem signal
Even when a confusing signal is included in the input signal, such as when a sine wave signal of 0112 is input, and vice versa, the effect of avoiding false detection of the training signal can be obtained.

[Brief explanation of drawings]

FIG. 1 is a principle block diagram showing the configuration of a modem training signal detector according to the present invention, FIG. 2 is a block diagram showing the configuration of a modem training signal detector according to an embodiment of the present invention, and FIG. 3 is an implementation of the present invention. FIG. 4 is a block diagram of a conventional modem training signal detector. In Figures 1 and 2, 1 is a carrier signal extraction means with a 1700Hz BPF, 2
3 is a phase-locked loop PLL circuit, 3 is a synchronous detection detection circuit, 4 is full power output means for input signals, 5 is upper limit frequency output means, and 6 is upper middle and lower frequency removal output means.

Claims (1)

[Claims] Carrier signal extraction means (1) for extracting a carrier frequency component of a modem signal from an input signal, and extraction in a limited frequency range around the carrier frequency extracted by the carrier signal extraction means (1). a possible phase-locked loop (2); and a carrier signal extracted from the input signal by the carrier signal extraction means (1) is synchronously detected by the output of the phase-locked loop (2), and a change in the DC component of the detection output is detected. a synchronous detection detection circuit (3) that outputs the signal power of all frequencies of the input signal, a total power output means (4) that outputs signal power of all frequencies of the input signal, and an upper limit frequency output means (5) that extracts the upper limit frequency component of the modem signal from the input signal. and upper/middle/lower frequency removal output means (6) for outputting signal power obtained by removing signals of the upper limit frequency, carrier frequency, and lower limit frequency of the modem signal from the input signal, and the total power output means (
4) and the output of the upper limit frequency output means (5); and a second comparator (8) for comparison, a third comparator (9) for comparing the output of the upper, middle and lower frequency removal output means (6) with a predetermined threshold α, and the synchronous detection detection circuit ( 3) output and the first comparator (7)
, the output of the second comparator (8), and the output of the third comparator (9) are simultaneously output for a certain period of time, the detection output means (10) outputs a detection output C. modem training signal detector.