JPS63228497A - semiconductor storage device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory device, and is a technology that is effective when applied to a semiconductor memory device such as a dynamic RAM having a page mode or static column mode function, for example. It is related to.

[Conventional technology]

There are dynamic RAMs that have page mode and static column mode functions. In such a dynamic RAM, a series of stored data can be input/output row by row at high speed by sequentially specifying a plurality of memory cells coupled to a selected word line.

Regarding dynamic RAM with a page mode function, for example, in September 1983, ■r published by Hitachi, Ltd.
It is described in Hitachi IC Memory Data Book J, pages 307 to 313.

[Problem that the invention seeks to solve]

It is conceivable to configure, for example, an image memory by taking advantage of the page mode function of the dynamic RAM described above. In this case, for example, by making the extending direction of the rows or word lines of the dynamic RAM correspond to the X-axis of the displayed image, high-speed input/output of image data in the X-axis direction becomes possible. However, when the correspondence is made as described above, the rows of displayed images, that is, the Y-axis corresponding to the extending direction of the data lines, cannot perform high-speed input/output operations of image data because the word lines cannot be switched at high speed. In addition, since the word line and data line of the dynamic RAM are fixedly associated with the X and Y axes of the display image, it is necessary to replace all image data if it is necessary to convert the coordinate axes of the display image. , the processing load on the image processing processor increases.

An object of the present invention is to provide a semiconductor memory device having new functions.

The above and other objects and novel features of this invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Means for solving problems]

A brief overview of typical inventions disclosed in this application is as follows.

That is, a memory array of a semiconductor memory device is comprised of memory cells arranged substantially in a lattice pattern in a storage space, each having two sets of address selection means, and memory cells substantially corresponding to the X-axis and Y-axis of the storage space, respectively. The X-axis word line and the Y-axis word line to which the control terminals of the address selection means of the corresponding memory cells are coupled are provided substantially at an inclination angle of 45 degrees to the X-axis and Y-axis of the storage space, respectively. It is composed of a data line and a data line.

[For production]

According to the above-mentioned means, since memory cells can be connected to data lines row by row in any direction of the X-axis and Y-axis of the storage space, stored data can be connected in any direction of the X-axis and Y-axis of the storage space. In addition to being able to input and output units at high speed, it is also possible to convert the coordinate axes of the storage space without replacing the stored data.

[Example 1] FIG. 5 shows a dynamic RA to which this invention is applied.
A block diagram of one embodiment of M is shown. Each circuit element in the figure is manufactured using known semiconductor integrated circuit manufacturing technology.
Although not particularly limited, it is formed on one semiconductor substrate such as single crystal silicon.

The dynamic RAM of this embodiment has a page mode function, although it is not particularly limited, and is used as a so-called image memory for displaying images. Furthermore, as will be described later, the dynamic RAM of this embodiment is provided with an X-axis word line and a Y-axis word line that are arranged substantially perpendicular to the storage space, and these X-axis word lines and An X-axis row address decoder RDCRx and a Y-axis row address decoder RDCR7 are provided corresponding to the Y-axis word line. Further, complementary data lines are provided so as to substantially form an inclination angle of 45 degrees to the X-axis word line and the Y-axis word line, respectively, and these complementary data lines are alternatively connected to the complementary common data line CD-. A column switch C8W is provided for connecting to 10,000.

A data line selection signal is supplied to this column switch C3W from a pointer PNT. This data line selection signal is sent to pointer P by column address decoder CDCH.
A logic "1" selection signal written to a predetermined bit of NT is formed by being cyclically shifted within the pointer PNT.

The dynamic RAM of this embodiment is supplied with a row address strobe signal and a write enable signal WE as control signals from the outside, and a row selection control signal R.
X/Y is supplied.

As a result, the dynamic RAM of this embodiment selects memory cells row by row in arbitrary directions of the X-axis and Y-axis of the memory array, and sequentially selects memory cells from the complementary common data line CD-τ.
It has a page mode function that inputs and outputs stored data at high speed by connecting to 10,000 units. At this time, the X-axis or Y-axis direction is specified according to the row selection control signal RX/Y, and the word line to be selected is specified according to the address signals AO to At. Further, after the row address strobe signal R and the column address strobe signal στ are once set to low level, only the column address strobe signal ττ is repeatedly changed from high level to low level, so that the logic “” set in the pointer PNT is changed. 1'' selection signal is shifted, and the column address is automatically switched.

Furthermore, the dynamic RAM of this embodiment is provided with an automatic refresh operation mode for autonomously refreshing the stored information of the memory cells, and at this time, a refresh address counter REFC and a refresh address counter REFC are provided for sequentially specifying word lines to be refreshed. , the address selection means ADB switches and selects the refresh address signals cO-ct formed by the refresh address counter REFC and the address signal AO-At supplied from the outside.
An address multiplexer AMX is provided for communicating.

In FIG. 5, the memory array M-ARY has 1-1+1 X-axis word lines arranged in the vertical direction in the figure, fi+1 Y-axis word lines arranged in the horizontal direction in the figure, n+1 sets of complementary data lines arranged at an inclination angle of 45 degrees with respect to the X-axis word line and the Y-axis word line, respectively, and arranged in a grid at the intersections of these X-axis word lines, Y-axis word lines, and complementary data lines. It is composed of (n+1)2(1!) dynamic seven-dimensional memory cells.

FIG. 1 shows a layout diagram of one embodiment of the memory array M-ARY of FIG. 5. In FIG. FIG. 2 also shows memory cells MC of the memory array M-ARY of FIGS. 5 and 1.
A circuit diagram of one embodiment is shown. Prior to explaining the circuit block of FIG. 5, the specific structure and operation of the memory array M-ARY and memory cell MC will be explained with reference to FIGS. 1 and 2.

In FIG. 1, the memory array M-ARY is arranged parallel to the fi+1 X-axis word lines WXO to W x n arranged in the vertical direction in the drawing and in parallel in the horizontal direction in the drawing. The memory array M-ARY includes fi+1 Y-wheel word lines WyO to Wyn, and the memory array M-ARY includes, but is not particularly limited to, These X
At the intersections of the axis word line, Y-axis word line, and complementary data line, memory cells MC:0.0 to M GO,n to M
Cn,O=M Cn,n are arranged in a grid.

Memory cells M CO,Q to M CO,n to MCn
, 0 to MCn,n are not particularly limited, but as representatively shown in the memory cells MCn,n in FIG. 2, they are each Ill! It includes an information storage capacitor Cs and two address selection MO3FETs (address selection means) Qmx and Qmy. The drains of the address selection MO3FETs Qmx and Q m y are connected in common, and are further coupled with a predetermined regularity to the non-inverted signal line or the inverted signal line of the corresponding complementary data lines DO·■ to Dn-Dn. Second
In the figure, memory cells MCn, n are connected to complementary data lines DO and D.
The case where the signal is coupled to the non-inverting signal line of O is shown by a solid line, and the case where it is coupled to the inverting signal line is shown by a dotted line.

MO3FETQ for address selection of memory cells MCn, n
The sources of mx and Qrny are similarly connected in common and further coupled to one electrode (input/output node) of the information storage capacitor Cs. A cell plate voltage Vc, which is a predetermined voltage, is applied to the other electrode of the information storage capacitor Cs.
p is supplied.

MO3FE T for address selection of memory cell MCn, n
The gate of Q m x is the corresponding X-axis word IJil
Coupled to Wxn. Similarly, the gates of the address selection MO3FETs Qmy of memory cells MCn, n are coupled to the corresponding Y-axis word line Wyn. X-axis word line Wx
Both the n- and Y-axis word lines Wyn are set to a logic low level when the dynamic RAM is in a non-selected state. Therefore, the address selection MO of memory cell MCn,n
S F E T Q m x and Qmy are both turned off, and memory cells MCn, n are placed in a non-selected state. On the other hand, when the dynamic RAM is in the selected state and the address signals AO to Ai are set to a corresponding combination,
Either the X-axis word line Wxn or the Y-axis word line Wyn is alternatively brought to a selected state of logic high level according to the row selection control signal RX/Y. This allows the address selection MOS FET Qm x or Qrny
is turned on, and memory cells MCn,n are connected to complementary data lines DO-DO.

As shown in FIG. 1, the X-axis word #ILW x O
~Wxn has corresponding fi+1 memory cells MCO,O~MCO,n to MCn,0''
MCn,n address selection MOS F'ET
The gates of Q m x are coupled in common. Similarly, Y
The axis word lines WyO-Wyn each have a corresponding fi
MO3FE for address selection of +1 memory cell M C0,0 to M Cn,O or MCO,n to Mcrt-n
The gates of TQmy are commonly coupled. Complementary data line D
For O/DO, the corresponding address selection MO3
Through F E T Q m x and Q m y, n
+ l (memory cells MC0,0, MC1,1,
...The input/output nodes of MCn,n are alternately coupled with a predetermined regularity. Similarly, complementary data line D1・■
n+1 memory cells M C0, 1 to M C0, 1 to M
Cn,0 to M CO,n =M Cn,n-1 input/output nodes are alternately coupled with a predetermined regularity.

X-axis word line WxO to W x n and Y-axis word line Wy
As shown in the above-mentioned X-axis word line Wxn and Y-axis word line Wyn, O-Wyn is all set to a logic low level when the dynamic RAM is in a non-selected state. In addition, these X-axis word lines and Y-axis word lines are
The dynamic RAM is in the selected state and the address signal A is
When O-At are set as corresponding combinations, one of them is alternatively set to a selected state of logic high level according to row selection control signal RX/Y. X-axis word line W
By alternatively setting either the x O-W
S F E T Q m x or Q m y is turned on. As a result, complementary data lines DO/DO=Dn-
One memory cell at an address corresponding to each word line is selectively connected to Dn.

Here, the addresses of the memory cells connected to the complementary data lines Do-DO to Dn and Dn differ depending on the row address of the selected word line.

That is, when the X-axis word line WXO of the X-axis row address O is brought into the selected state, the complementary data line Dc-Dτ of the column address C has the memory cell MCO.

C is connected, and the column address of the complementary data line and the Y-axis row address of the memory cell are sequentially associated with each other. Similarly, when the X-axis row address aOX-axis word line Wxa is set to the selected state, the complementary data line D of the column address C
c−Dτ has memory cells MCa, c+a (here,
Row address and column address operations are performed with the module being n.

(the same applies hereinafter) are connected, and the column addresses of the complementary data lines and the Y-axis row addresses of the memory cells are sequentially correlated. In other words, the X-axis row address aOX-axis word line W x
When a is in a selected state, the memory cell MCa is arranged at the first Y-axis row address among the memory cells coupled to the X-axis word line.

0 is complementary data line D of column address (n-a+l)
na+1 and Dn-a+1, and the other memory cells are connected so that the Y-axis row address of the memory cell and the column address of the complementary data line are sequentially associated with each other.

On the other hand, when the Y-axis word line WyO at the Y-axis row address 0 is selected, the complementary data line D at the column address C
A memory cell MCn-c+1.0 is connected to c-Dc, and the column address of the complementary data line and the X-axis row address of the memory cell are associated in reverse order. Similarly, when the Y-axis word line Wyb at the Y-axis row address b is set to the selected state, the complementary data line DC-Dτ at the column address C has the memory cell MCn-c+1+b,b, that is, the memory cell MCb-c, b is connected, and the column address of the complementary data line and the X-axis row address of the memory cell are associated in reverse order. In other words, when the Y-axis word line wyb at the Y-axis row address b is brought into the selected state, the first l! of the memory cells coupled to the Y-axis word line are selected. The memory cell MCO,b arranged at the IIX-axis row address is connected to the complementary data line Db-Db of the column address b, and the other memory cells are arranged so that the X-axis row address of the memory cell and the column address of the complementary data line are Connected so that they are associated in reverse order.

The correspondence between these row addresses and column addresses is the key point for defining the start address and selection direction of the selection operation by the column switch CSW, pointer PNT, and column address decoder CDCH, which will be described later.

In FIG. 5, X constituting the memory array M-ARY
Axis word lines WxO to Wxn are coupled to an X-axis row address decoder RDCRx, and one of them is selected and designated. This X-axis row address decoder RDCRx has
Complementary internal address signal aQxai (here, for example, external address signal A
An internal address signal aO having the same phase as O and an internal address signal aO having the opposite phase are collectively expressed as a complementary internal address signal 1o (the same applies hereinafter), and a timing signal φwx is supplied from a timing control circuit TC, which will be described later. Ru.

This timing signal φl+IX is the dynamic type RA
When the logic low level is set in the non-selected state of M, the dynamic RAM is put into the selected state and the row selection control signal RX/
When the X-axis word line is designated by Y, it is set to a logic high level at a predetermined timing.

The X-axis row address decoder RDCRx receives a complementary internal address signal aQx supplied from the address buffer ADB.
ai, and according to the timing signal -NX supplied from the timing control circuit TC, the X-axis word! J.I.
One of WXO to Wxn is alternatively set to a high level selection state.

Similarly, the Y-axis word lines W70 to Wyn constituting the memory array M-ARY are connected to the Y-axis row address decoder RDCR.
7, and one of them is selected and designated. This Y-axis row address decoder RDCR7 is supplied with complementary internal address signals 10-11 from address buffer ADB, and also supplied with timing signal φNY from timing control circuit TC. This timing signal φ is
It is set to a logic low level when the dynamic RAM is in a non-selected state, and set to a logic high level at a predetermined timing when the dynamic RAM is set to a selected state and the Y-axis word line is specified by the row selection control signal RX/Y. .

Y-axis row address decoder RDCR7 receives complementary internal address signal 10 supplied from address buffer ADi3.
- decodes the Y-axis word line W according to the timing signal φwy supplied from the timing control circuit TC.
70 to Wyn are alternatively set to a high level selection state.

On the other hand, complementary data I constituting the memory array M-ARY
dADO·Dingτ~Dn-101 is coupled to one of the corresponding switch MO3FET pair of the column switch C3W through the corresponding unit circuit of the sense amplifier SA.

The sense amplifier SA is composed of fi+1 unit circuits that correspond to each complementary data line and are gated. Each unit circuit of the sense amplifier SA consists of two sets of CMOs that are cross-connected.
It is constituted by a flipflop 7 block consisting of an S impark circuit, and its input/output nodes are respectively coupled to the non-inverted signal line and the inverted signal line of the corresponding complementary data line. These unit circuits of the sense amplifiers SA are memory devices coupled to the selected X-axis word line or Y-axis word line that are activated all at once by the high level of the timing signal φpa supplied from the timing control circuit TC. The minute read signal output from the cell to the corresponding complementary data line is
The signal is amplified by the corresponding unit circuit of the sense amplifier SA and converted into two signals of high level or low level.

The sense amplifier SA includes, but is not particularly limited to, a precharge circuit for shorting both signal lines of the complementary data line and setting the level to a half precharge level that is approximately 1/2 of the power supply voltage Vcc. The provision of this precharge circuit speeds up the level change of the complementary data line, and speeds up the read operation of the dynamic RAM.

The column switch C3W is constituted by fi+1 switch MO5FET pairs provided corresponding to each complementary data line. One of these switch MO3F B 'T' pairs is connected to the corresponding complementary data line DO/
DO~1) is connected to the n-Dt line, and the other is commonly connected to the inverted signal line CD and the inverted (i9 line τ) of the complementary common data line.

Furthermore, the gates of each pair of switch MOS FETs are connected in common, and the corresponding data line selection signals YO to Yn are supplied from the pointer PNT. Thereby, the column switch C3W selectively connects a set of complementary data lines designated by the data line selection (N numbers YO to Yn) and the common complementary data line CD-ter.

The pointer PNT has a basic configuration of an n+1 bit shift register that can be shifted in both directions. The final focus of this shift register is coupled to its first bit via signal line 3b. The pointer PNT receives a timing signal φSC for shift clocking from the timing control circuit TC.
and a timing signal φxy for controlling the shift direction.
is supplied. Of these, the timing signal φsc is normally set to a logic low level, and is temporarily set to a logic high level each time an input/output operation of storage data in page mode is completed. Furthermore, the timing signal φxy is set to a logic low level when the dynamic RAM is in a non-selected state, and is selectively set to a logic low level when the dynamic RAM is in the iM abundance state and the X-axis word line is specified by the row selection control signal RX/Y. Considered to be a logical high level.

The output signal of the corresponding bit of the column address decoder CDCH is supplied to the input terminal of each bit of the shift register constituting the pointer PNT. Also, pointer P
The output signal of each bit of NT is the data line selection signal YO~
Yn is supplied to the gates of the corresponding switch MO3FET pairs of the column switch C8W.

The column address decoder CDCR is supplied with the complementary internal address signal aQxai from the address buffer ADH, and is also supplied with the timing signal φxy and the timing signal φps for setting a shift signal in the pointer PNT from the timing control circuit TC. .

The column address decoder CDCR receives complementary internal address signals 3-0 to - supplied from the timing control circuit TC.
It decodes a-i and selectively outputs a logic high level output signal, that is, a shift signal of logic "1" to the corresponding bit of the pointer PNT.

The output signal of the column address decoder CDCR specifies the first bit for starting the shift operation of the pointer PNT, and is the first Y-axis row address or This designates the memory cell placed at the X-axis row address.

As mentioned above, the column address of the complementary data line to which the memory cell placed at the first Y-axis row address or X-axis row address is connected is determined by the column address of the complementary data line connected to the X-axis word line according to the row selection control signal RX/Y, that is, the timing signal φxy. or the Y-axis word line is specified and the address signal AO
~Ai, that is, it depends on whether the row address of the X-axis word line or the Y-axis word line is specified according to the complementary internal address signal O-i. Therefore, the column address decoder CDCR determines the first Y-axis row address or the first X-axis row address based on the timing signal φxy and complementary internal address signals ao to ai, and selects the corresponding output signal according to the timing signal φps. Uniformly set to a high level of logic.

A logic “1” placed in a predetermined bit of pointer PNT
” is cyclically shifted one bit at a time according to the timing signal φsc supplied from the timing control circuit TC. At this time, the shift direction is determined by the timing signal φxy supplied from the timing control circuit TC.
determined according to In other words, as described above, depending on which of the X-axis word line and Y-axis word line is selected, the column address of the complementary data line and the Y-axis row address of the memory cell connected to these complementary data lines or the Axis row addresses are associated and connected in order or in reverse order. Therefore, the shift direction of the pointer PNT is switched according to the timing signal φxy, and control is performed so that the selection order of complementary data lines is the Y-axis row address order or the X-axis row address order of the memory cells coupled to the selected word line. are doing.

By cyclically shifting the logic '1' shift signal in the pointer PNT, the data line selection signal YO
-Yn is sequentially set to a logic high level, and the corresponding complementary data lines are successively connected to the complementary common data line CD-ζ100. This allows % for n + i memory cells coupled to the selected X-axis or Y-axis wordline
n+1 bits of stored data are input and output in a predetermined order.

Memory array M-ARY by column switch C8W
The complementary common data line CD-ττ, to which the complementary data lines Do-DO to Dn-Dn are selectively connected, is coupled to the input terminal of the main amplifier MA and the output terminal of the data input buffer DIB. Ru. Main amplifier M
The output terminal of A is further coupled to the input terminal of a data output buffer DOB.

The main amplifier MA is selectively activated by the timing signal φa supplied from the timing control circuit TC, and the complementary data line and the complementary common data line CD- are input from the selected memory cell of the memory array M-ARY. C
The binary readout signal outputted via D is further amplified and transmitted to the data output cover 7-FA DOB.

In the read operation mode of the dynamic RAM, the data output buffer DOB is connected to the timing control circuit TC.
It is selectively activated by a timing signal φoe supplied from the main amplifier MA, and outputs a memory cell read signal transmitted from the main amplifier MA to an external device via a data output terminal Do. In the non-selected state and write operation mode of the dynamic RAM in which the timing signal φoe is at a low level, the output of the data output buffer DOB is brought into a high impedance state.

In the write operation mode of the dynamic RAM, the data input cover sofa DIB controls the timing control circuit TC.
It is selectively put into an operating state by a timing signal φHe supplied from the terminal φHe, and inputs write data supplied from an external device via the data input terminal DI. ! It is used as a write signal and is supplied to the complementary common data line CD-CD. In the non-selected state and read operation mode of the dynamic RAM in which the timing signal φwe is at a low level, the output of the data driver sofa DIB is brought into a high impedance state.

Address buffer ADB is supplied with a row address signal from address multiplexer AMX, and is also supplied with timing signal φa3 from timing control circuit TC. Address buffer ADB takes in and holds a row address signal transmitted from address multiplexer AMX in accordance with the timing signal φas. Also, complementary internal address signals are generated based on these row address signals! 0~! ■ forms an X-axis row address decoder R
DCRx, Y-axis row address decoder RDCRy, and column address decoder CDCH.

In the automatic refresher mode in which the timing signal φref supplied from the timing control circuit TC is at a high level, the address multiplexer AMX selects the refresh address signals CO to ci supplied from the refresher address counter REFC and outputs a row address signal. It is transmitted to the address buffer ADB as the address buffer ADB. Further, in normal memory access when the timing signal φref is at a low level, the address signal AO-At supplied via the external terminals AO to Ai is selected and transmitted to the address buffer ADB as a row address signal.

The refresh address counter REFC receives a timing signal φrc supplied from the timing control circuit TC in the automatic refresh mode of the dynamic RAM.
A refresh address signal cOxci for sequentially specifying word lines to be refreshed is formed and supplied to an address multiplexer AMX. In the automatic refresh mode, although not particularly limited, the X-axis word lines WxO=Wxn are sequentially selected by the refresh address signals cO to ci,
A refresh operation of data stored in the memory cell is performed.

The timing control circuit TC receives a row address strobe signal, a column address strobe signal CAS, and a write enable signal W supplied from the outside as control signals.
The various timing signals mentioned above are formed based on E and the row selection control signal RX/Y, and are supplied to each circuit.

FIG. 6 shows a timing chart of an embodiment of a page mode read operation of the dynamic RAM of this embodiment. In this embodiment, the X-axis row address a
The X-axis word line Wxa is selected, and the memory cell M
The operation is exemplarily shown when fi+l bit data stored in Ca, ONM Ca, n is read out continuously in page mode.

In FIG. 6, the dynamic RAM is activated by changing the row address strobe signal RAS from a logic high level to a logic low level, although this is not particularly limited. Prior to the fall of the row address strobe signal RAS to the logic low level, the write enable signal WE is set to the logic high level to designate the read operation mode. Similarly, row selection control signal R
X/Y is set to an extremely high level, and it is specified that this page mode is to be performed from the X-axis word line direction. In addition, external terminals AO to At are provided with address signals AO to At in a combination that specifies the X-axis row address a.
is supplied.

In a dynamic RAM, a timing signal φas is formed by setting a row address strobe signal RAS to a logic low level, and external address signals AO to Ai are taken into an address buffer ADB. Furthermore, since the row selection control signal RX/Y is at the write margin high level at the falling edge of the row address strobe signal πτ, the timing signal φxy6 is set to be at the logic high level. When the row selection control signal RX/Y is set to the logic low level at the falling edge of the row address strobe signal RAS, in the dynamic RAM, the timing signal φxy is set to the logic low level as shown by the dotted line in FIG. A Y-axis word line selection operation is performed.

Furthermore, in dynamic RAM, the timing signal φ
The timing signal φHX is set to a logic high level a little later than as, and the timing signal φpa is set to a logic high level a little later than the timing signal φwx. This allows the X-axis row address decoder RDCRx to
The selection operation of the axis word line is started, and the X-axis word line Wxa
is alternatively set to a high level selection state. Complementary data lines DO/DO=Dn-Dn include fi+1 memory cells MCa, 0 to MC coupled to the X-axis word line Wxa:
a.

A minute read signal according to the stored data of n is output,
Each signal is amplified by a corresponding unit circuit of the sense amplifier SA.

After a predetermined time has elapsed since the fall of the row address strobe signal RAS, the column address strobe signal CAS is changed from a logic high level to a logic low level. In a dynamic RAM, the timing signal φ is triggered by the fall of the column address strobe signal CAS.
p3 is set to logic high level for a predetermined time, and after a slight delay, timing signals φma and φoe are set to logic high level one after another. As a result, first, the output signal of the bit corresponding to the column address (n-a+l) of the column address decoder CDCRO becomes a logic high level alternatively, and a shift signal of logic "1" is set in the corresponding bit of the pointer PNT. . Further, by sending this shift signal of logic "1", the output signal of the corresponding bit of pointer PNT, that is, data line selection signal Yn-a+1 becomes logic high level, and complementary data 1illDn-n+
1 ・Dn-n+1 is connected below the complementary common data line CD-τ. As a result, read signals from memory cells MCa and O arranged at the first Y-axis row address among the memory cells connected to the X-axis word line Wxa are transmitted to the main amplifier MA via the complementary common data line CD-τ. is transmitted and amplified. The output signal of main amplifier MA is further sent out from data output buffer DOB via data output terminal Do by setting timing signal φoe to a logic high level.

Next, while the row address strobe signal RAS is kept at the logic low level, the column address strobe signal CAS is
is returned to a logic high level and then repeatedly changed from a logic high level to a logic low level at predetermined time intervals.

In the dynamic RAM, the timing signal φoe is returned to the logic low level by returning the column address strobe signal CAS from the logic low level to the logic high level, and the timing signal φsc is kept at the logic high level for a predetermined time. As a result, the output of the data output buffer DOB is placed in a high impedance state, and the shift signal of logic "1" placed on the pointer PNT is shifted forward by one bit. Therefore, the complementary data line [) n-n+2 ・Dn-n+2
is connected to complementary common data line CD-8, and the read signal of memory cell MCa, 1 is transmitted to main amplifier MA and amplified via complementary common data line CD-CD.

At the second falling edge of the column address strobe signal CAS, in the dynamic RAM, the timing signal φoe is set to the logic no 1 level again. As a result, the data stored in the memory cell MCa,1 is sent out from the data output sofa DOB via the data output terminal Do.

Thereafter, as the column address strobe signal CAS is repeatedly changed from a logic high level to a logic low level, the timing signal ψO
e and φsc are repeatedly brought to the logic level. As a result, pointer PNT is shifted in the forward direction one bit at a time, and the stored data of memory cells iCa, 2 to MCa, n are sequentially sent out from data output terminal DO.

When the row address strobe signal RAS and the column address strobe signal CAS are returned to the logic high level at the same time, in the dynamic RAM, the timing f words φXL φwx, φPa+ φ−a and φoe become the logic low level at the same time, and the dynamic RAM becomes unselected.

By the way, when the row selection control signal RX/Y is set to the logic low level at the falling edge of the row address strobe signal RAS to the logic low level, as shown by the dotted line in FIG. Instead, the timing signal φwy is set to a logic high level.As a result, in the dynamic RAM, the Y-axis word line Wya at the Y-axis row address a is selected, and the Y-axis word line Wya is connected to this Y-axis word line Wya. n + 1-valent memory cells M CO,a to M Cn
, a are output continuously at high speed. At this time, a shift signal of logic "1" is sent to the bit corresponding to column address a of pointer PNT, and this shift signal is shifted in the opposite direction according to timing signal φ3C.

As described above, the memory array M-ARY of the dynamic RAM of this embodiment has (n+1) two memory cells each having 2(il) MO3FETs for address selection, and corresponding memory cells arranged orthogonally. n+1 X-axis word lines WxO to Wxn and Y-axis word lines wyo to which the gates of the address selection MOS FETs are coupled.
Wyn, and fi+1 sets of complementary data lines DO/DO to Dn-Dn arranged at an inclination angle of 45 degrees to the X-axis word line and Y-axis word line, respectively. The dynamic RAM is activated, and the column address strobe fδ CAS is repeatedly changed from a logic high level to a logic low level while keeping the row address strobe signal positive τ1 at a logic low level.
X-axis word line WxO according to row selection control signal RX/Y''
~Wxn or one of the Y-axis word lines WyO~Wyn is alternatively set to a high level selection state, and fi+1 memory cells coupled to that word line are sequentially connected to the complementary data lines DO/Cho~ Connected to Dn and Dn. These H+1 memory cells are connected to a complementary common data line CD-
500, storage data in row units is input/output in the order of the X-axis row address or the Y-axis row address. As a result, the dynamic RAM of this embodiment has a storage space of X
It is possible to input and output stored data in units of rows at high speed from any direction along the axis or the Y axis, and it is possible to speed up the transfer of display 'fs images, etc., for example.

[Embodiment 2] Fig. 3 shows a dynamic type RA to which this invention is applied.
A layout diagram of another embodiment of M memory array M-ARY is shown. In this embodiment, the other circuit blocks except the memory array M-ARY are the same as those in the first embodiment described above, and a description of their configuration and operation will be omitted.

In FIG. 3, the memory array M-ARY includes n+1 X-axis word lines WxO to WxO arranged in the vertical direction in the figure.
Wxn and fi+1 sets of complementary data lines Do-D-Dn.On arranged in the horizontal direction of the figure are provided. In addition, 4 lines are connected to each of these X-axis word lines and complementary data lines.
With a tilt angle of 5 degrees, n+1 Y-axis word lines WyO
-Wyn is provided. At the intersections of these X-axis word lines, Y-axis word lines, and complementary data lines, there are (n+1) two memory cells MC0,0 to MGO,n to MCn,0.
~MCn,n is arranged.

FIG. 4 shows a circuit diagram of one embodiment of the memory cell of the memory array M-ARY of FIG. 3.

Before proceeding with the explanation of the memory array M-ARY in FIG.
An overview of the configuration and operation of the RY memory cell will be explained. Fourth
Fl! J has an X-axis word line Wxn and a Y-axis word line W.
A memory cell MCn,n arranged at the intersection of yn is exemplarily shown.

The memory cells of the memory array M-ARY of this example are:
The structure is similar to that of the memory cell MC of the memory array M-ARY of the embodiment shown in FIG. That is, memory array M
-ARY each memory cell is the memory cell MCn of FIG.
, n, a 1ull information storage capacitor C3 and a HIM address selection MO
The drains of MO3FETs Qmx and Qmy for address selection, including 3FET (address selection means) Qmx and Qmy, are commonly connected, and are further connected to the non-inverted signal line or inverted signal line of the corresponding complementary data lines DO-Do to Dn-Dn. are combined with a predetermined regularity. In FIG. 4, the case where the memory cell MCn,n is coupled to a non-inverted signal line of the complementary data lines DO/DO is shown by a solid line, and the case where it is coupled to an inverted signal line is shown by a dotted line. memory cell MC
MOS FET Q m for address selection of n and n
The sources of x and Q m y are similarly connected in common,
Furthermore, it is coupled to one electrode (input/output node) of the information storage capacitor C3.

A cell plate voltage VCp, which is a predetermined voltage, is supplied to the other electrode of the information storage capacitor Cs.

MO3FE T for address selection of memory cell MCn, n
The gate of Q m x is connected to the corresponding X-axis word line Wxn
is combined with Similarly, the gates of the address selection MO3FETs Qmy of memory cells MCn, n are coupled to the corresponding Y-axis word line Wyn. The memory cells MCn,n are brought into a selected state by selectively turning on the address selection MO3FETs Qmx and Qmy of the memory cells MCn,n according to the corresponding X-axis word line Wxn or Y-axis word line Wyn. , whose input/output nodes are coupled to the non-inverted signal line or inverted signal line of the corresponding complementary data lines DO and Do.

As exemplarily shown in FIG.
O=W x n has corresponding fi+1 memory cells MCO,0 to MCO,n to MCn, respectively.
.

The gates of MO3FETQmX for address selection of 0 to MCn, n are commonly coupled. Similarly, Y-axis word line Wy
O to Wyn have corresponding n+1 memory cells M C0,0 to M Cn,0 to MCO,n = M
The gates of the address selection MO3FETQmy of Cn and n are commonly coupled.

The memory cells coupled to the X-axis word line and the Y-axis word line are connected to complementary data lines DO/Dn-Dn in the same combination as in the first embodiment described above when each word line is in a selected state. In other words, each complementary data line DO is connected to a corresponding address selection MOS FET Qm.
x and Q m y through fi+1 memory cells MCO,O, MC1,1.

...The input/output nodes of MCn,n are alternately coupled with a predetermined regularity. Similarly, complementary data lines D1 and D
I-Dn-Dn is connected to n+1 memory cells MC0゜1 to MC through corresponding address selection MOS FET Qm x and Qm y, respectively.
Input/output nodes from n, 0 to M CO, n - M Cn, n-1 are alternately coupled with a predetermined regularity.

Furthermore, among the fi+1 memory cells coupled to each X-axis word line, the column addresses of the memory cells to which the first BY-axis row address is assigned are shifted one by one.

X-axis word lines WxO to Wxn and Y-axis word line WyO-
Wyn is alternatively set to a high level selected state as in the case of the first embodiment described above, and one corresponding n+4-valent memory cell is placed on each of the complementary data lines DO and DO to Dn-Dn. For example, when the X-axis word line WxO of the X-axis row address 0 is selected, the memory cell M is connected to the complementary data/evening line Dc-Dc of the column address C.
CO and c are connected, and the column address of the complementary data line and the Y-axis row address of the memory cell are sequentially correlated.

Similarly, when the X-axis word line Wxa of the X-axis row address a is set to the selected state, the complementary data lines Dc-Dc of the column address C have memory cells M Ca,c0a7! l(
The column addresses of the complementary data lines and the Y-axis row addresses of the memory cells are sequentially associated with each other. In other words, X
When the X-axis word line W x a at the axis row address a is brought into the selected state, the memory cell MCa is arranged at the first Yfio row address among the memory cells coupled to the X-axis word line.

O is the column address (as in the first embodiment described above).
n-n+1) complementary data line Dn-a+1 ・Y)n
-n+1, and the other memory cells are connected so that the Y-axis row address of the memory cell and the column address of the complementary data line are sequentially associated with each other.

On the other hand, when the Y-axis word line WyO at the Y-axis row address 0 is selected, the complementary data line D at the column address C
A memory cell MCn-c+1.0 is connected to c-Dc, and the column address of the complementary data line and the X-axis row address of the memory cell are associated in reverse order. Similarly, when the Y-axis word line wyb at the Y-axis row address b is set to the selected state, the complementary data line D'c-Dc at the column address C has memory cells M Ca-c+1+b, b, that is, memory cells MCb-c , b are connected, and the column addresses of the complementary data lines and the X-axis row addresses of the memory cells are associated in reverse order. In other words, when the Y-axis word line W7b at the Y-axis row address b is brought into the selected state, the memory cell MCO,b arranged at the first MX-axis row address among the memory cells coupled to the Y-axis word line is Similar to the first embodiment described above, the other memory cells are connected to the complementary data line Db-D of column address b, and the X-axis row address of the memory cell and the column address of the complementary data line correspond in reverse order. Connected to be attached.

Konomi Jr! The example memory array M-ARY can be used as is in the dynamic RAM shown in FIG. 5 by replacing the memory array M-ARY of the first embodiment shown in FIG. , it is possible to perform input/output operations for stored data on a line-by-line basis in page mode.

As described above, in the dynamic RAM memory array M-ARY of this embodiment, logically, as in the first embodiment, the X-axis word line and the Y-axis word line are provided orthogonally. 4 each for the X-axis word line and Y-axis word line.
Complementary data lines are provided with a 5 degree tilt angle. However, in the actual layout, the X-axis word line WxO
~Wxn and the complementary data line DO/Dn-Dn-Tau are arranged orthogonal to each other, and the Y-axis word line W7 is connected to the X-axis word line and the complementary data line with an inclination angle of 45 degrees, respectively.
0 to Wyn are arranged. Also, at the intersection of these X-axis word lines, Y-axis word lines, and complementary data lines, (n+1)
2 memory cells are connected to the aforementioned first memory cell for each complementary data line.
The memory cells are arranged with a predetermined regularity so that the same combinations of memory cells as in the embodiment are connected. therefore,
In the dynamic RAM of this embodiment, as in the first embodiment described above, storage data can be input/output in units of rows at high speed from any direction of the X-axis or Y-axis of the storage space. Furthermore, the dynamic RAM of this embodiment
Here, the complementary data lines DO.DO to Dn.nu.n are arranged to have the same length in the horizontal direction of the memory array M-ARY. Therefore, the loads caused by parasitic charges and wiring resistance on the complementary data lines DO-DO to Dn-5 are equalized.
The serial input/output operation of the dynamic RAM is stabilized.

As shown in the above two embodiments, when the present invention is applied to a semiconductor integrated circuit device such as a dynamic RAM having a page mode or column static mode function, the following effects can be obtained. That is, (1) the memory array is comprised of a plurality of memory cells that are substantially arranged in a lattice shape in the storage space and each has two sets of address selection means, and that the memory array corresponds to the X-axis and Y-axis of the storage space, respectively. A plurality of X-axis word lines and Y
The axis word line and the corresponding address of the corresponding axis are provided substantially at an inclination angle of 45 degrees to the X axis and Y axis of the storage space, respectively, and one of the X axis word line or the Y axis word line is specified. The input/output nodes of a plurality of memory cells are configured with a plurality of data lines that are selectively coupled via corresponding address selection means, so that input/output nodes of a plurality of memory cells can be connected row by row in any direction of the X-axis and Y-axis of the storage space. The memory cells can be connected to the data lines by using the method, and storage data can be input/output in units of rows at high speed in any direction of the X-axis and Y-axis of the storage space.

(2) The above item (L) is increased by 5, and the effect of speeding up the input/output operation of both image data and the like to a dynamic RAM used for, for example, an image memory can be obtained.

(3) The above item <i> provides the effect that the coordinate conversion operation of the storage space can be performed at high speed without replacing the stored data stored in the memory.

(4) Items (11 to (3)) above provide the effect that the processing load on an image processing processor provided outside the semiconductor storage device can be reduced.

(5) In items (1) to (4) above, the X-axis word line and complementary data line are laid out orthogonally, and each of the X-axis word line and complementary data line is laid out at an angle of 45 degrees to the Y-axis. By laying out the word lines, the complementary data lines can be made to the same length to equalize loads such as parasitic capacitance and wiring resistance, which has the effect of stabilizing the serial input/output operation of dynamic RAM. It will be done.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that this invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. For example, in the dynamic RAM of this embodiment, the X-axis word line or Y-axis word line remains selected while the page mode is performed, but a data latch is provided before the column switch C8W. In the dynamic RAM of this embodiment, it is possible to perform memory access and serial input/output operations independently by
Serial output operation is progressing by repeatedly changing f1%CAS from high level to low level,
A clock signal for serial input/output may be provided separately, and the serial input/output operation may be performed using this clock signal.In addition, in this embodiment, an address signal AO-Al supplied as a row address signal may be used. Although the column address is automatically specified, serial input/output operations may be started from any column address by supplying a column address signal externally. Various embodiments can be adopted, such as the arrangement of the memory array shown, the specific circuit configuration of the memory cells shown in FIGS. 2 and 4, the block configuration of the dynamic RAM shown in FIG. 5, and the combination of control signals. It's Chino.

The above explanation will mainly focus on the dynamic type RA, which is the application field that is the background of the invention made by the present inventor.
Although the description has been made for the case where it is applicable to M, it is not limited thereto (for example, it can also be applied to various semiconductor memory devices such as static RAM). It can be widely applied to semiconductor memory devices that perform input/output operations.

〔Effect of the invention〕

WRj! describes the effects obtained by typical inventions disclosed in this application. The explanation for I is as follows. In other words, the memory array includes memory cells having two sets of address selection means, an X-axis word line and a Y-axis word line that substantially correspond to and are orthogonal to the X-axis and Y-axis of the storage space, respectively; The X-axis and Y-axis of the storage space are constructed with data lines provided at an inclination angle of 45 degrees respectively to the X-axis and Y-axis of the storage space.
A semiconductor memory device that can input and output stored data in row units in any axis direction at high speed, and that can perform coordinate transformation operations of storage space at high speed without replacing stored data stored in memory. It is.

[Brief explanation of drawings]

Figure 1 shows a dynamic RAM to which this invention is applied.
FIG. 2 is a circuit diagram showing an example of the memory cell of the memory array shown in FIG. 1, and FIG. 3 is a layout diagram showing an example of the memory array of FIG. , dynamic type R where light is commonly used.
FIG. 4 is a layout diagram showing another embodiment of the memory array of AM; FIG. 4 is a circuit diagram showing one embodiment of the memory cell of the memory array of FIG. 3; FIG. A block diagram showing an embodiment of a dynamic RAM including a memory array of FIG. 6 is a timing chart showing an embodiment of a read operation in the page mode of the dynamic RAM of FIG. M-ARY---Memory array, W x O ~ W xn
...X-axis word line, WyO~Wyn...Y-axis word line, Do・DO”Dn-Dn --・Complementary data line,
MC0,0~MCn,n...Memory cell, Cs...
- Information storage capacitor, Qmx, Qmy...MO3FET for address selection. SA...Sense amplifier circuit, C8W...Column switch, PNT...Pointer, CDCR...Column address decoder, RDCRx...X-axis row address decoder, RDCRy...Y-axis row address decoder, A
DB: address buffer, AMX: address multiplexer, MA: main amplifier, DIB: data input cover sofa, DOB: data output cover sofa, R
EFC...Refresh address counter, TC...
・Timing control circuit. Figure 3 Figure 4 Figure 5 Figure 6

Claims (1)

[Scope of Claims] 1. A plurality of memory cells each having two sets of address selection means provided substantially in a grid pattern in the storage space, and substantially corresponding to the X-axis and Y-axis of the storage space, respectively. a plurality of X-axis word lines and a Y-axis word line, which are provided in a plurality of X-axis word lines and a plurality of Y-axis word lines, to which control terminals of corresponding address selection means of a plurality of memory cells at corresponding addresses of respective axes are commonly coupled;
Substantially, each of the X-axis and Y-axis of the storage space is provided with an inclination angle of 45 degrees, and by specifying one of the X-axis word line or Y-axis word line, a plurality of corresponding addresses on the corresponding axis can be read. 1. A semiconductor memory device comprising a memory array comprising a plurality of data lines to which input/output nodes of memory cells are selectively coupled via corresponding address selection means. 2. The X-axis word line and the data line are arranged orthogonally, and the Y-axis word line is arranged at an inclination angle of 45 degrees with respect to the X-axis word line and the data line, respectively. A semiconductor memory device according to claim 1. 3. The semiconductor memory device continuously and serially inputs and outputs stored data to and from a plurality of memory cells that are brought into a selected state by designating one of the X-axis word line or the Y-axis word line. A semiconductor memory device according to claim 1 or 2, characterized in that the semiconductor memory device has a function of: