JPS63236406A - Pulse generation circuit - Google Patents

Pulse generation circuit

Info

Publication number
JPS63236406A
JPS63236406A JP62070717A JP7071787A JPS63236406A JP S63236406 A JPS63236406 A JP S63236406A JP 62070717 A JP62070717 A JP 62070717A JP 7071787 A JP7071787 A JP 7071787A JP S63236406 A JPS63236406 A JP S63236406A
Authority
JP
Japan
Prior art keywords
circuit
capacitor
pulse
variable resistors
resistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62070717A
Other languages
Japanese (ja)
Inventor
Akihiko Nakamura
明彦 中村
Takashi Miura
隆 三浦
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP62070717A priority Critical patent/JPS63236406A/en
Publication of JPS63236406A publication Critical patent/JPS63236406A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To simplify constitution and to control pulse width and a duty ratio, by inserting two variable resistors in a multivibrator constituted of a NAND circuit and two inversion circuits. CONSTITUTION:The variable resistors 26 and 27 are used as resisters which constitute the RC charge/discharge circuit of the multivibrator consisting of one NAND circuit 21 and the two inversion circuits 22 and 23 connected in series, and one ends of the two variable resistors 26 and 27 are connected to the output terminal of the inversion circuit 23 via diodes 24 and 25 set in reverse directions to each other, and the other ends to the input side of the inversion circuit 23 via a capacitor 28. A time constant at the time of charging the capacitor 28 is decided by the variable resistor 26 and at the time of discharging, it is decided by the variable resistor 27, therefore, it is possible to control the width T1 of a generated pulse signal and the generation interval T2 of a pulse independently respectively and freely.

Description

【発明の詳細な説明】 〔概 要〕 従来のパルス発生回路はパルス幅とデユーティ比を別個
に制御することが困難であった。そこでマルチバイブレ
ークに2個の可変抵抗を挿入し、パルス幅とデユーティ
比を自由に制御できるパルス発生回路の簡略化を図った
ものである。
[Detailed Description of the Invention] [Summary] In conventional pulse generation circuits, it is difficult to control the pulse width and duty ratio separately. Therefore, two variable resistors are inserted into the multi-by-break to simplify the pulse generation circuit, which allows the pulse width and duty ratio to be freely controlled.

〔産業上の利用分野〕[Industrial application field]

本発明は電磁継電器に内蔵される制御回路に係り、特に
パルス幅とデユーティ比を自由に制御できるパルス発生
回路に関する。
The present invention relates to a control circuit built into an electromagnetic relay, and more particularly to a pulse generation circuit that can freely control pulse width and duty ratio.

電磁継電器は半導体集積回路等からなるスイッチング素
子に比べ、比較的大きい電流を容易に制御できるという
利点があり、各種電子機器の制御回路に組み込まれて使
用されている。しかし半導体集積回路等からなるスイッ
チング素子と異なり、それを制御するための専用の制御
回路を必要とし使い難いという問題がある。そこでかか
る問題を解決する手段として制御回路を内蔵した電磁継
電器の開発が進められている。
Electromagnetic relays have the advantage of being able to easily control relatively large currents compared to switching elements made of semiconductor integrated circuits, etc., and are used by being incorporated into control circuits of various electronic devices. However, unlike a switching element made of a semiconductor integrated circuit or the like, there is a problem in that it requires a dedicated control circuit to control it and is difficult to use. As a means to solve this problem, electromagnetic relays with built-in control circuits are being developed.

しかし用途によって動作時間や停止時間が大幅に変わる
電磁継電器を制御する回路は、パルス幅とデユーティ比
を自由に制御できると共に、限られた空間に組み込むた
めに構成が簡単なパルス発生回路を具えていなければな
らない。そこで構成が簡単でパルス幅とデユーティ比を
自由に制御でき、しかも価格の安いパルス発生回路の実
現が望まれている。
However, the circuits that control electromagnetic relays, whose operating and stopping times vary greatly depending on the application, can control the pulse width and duty ratio freely, and are equipped with pulse generation circuits that can be easily configured to fit into limited spaces. There must be. Therefore, it is desired to realize a pulse generation circuit that has a simple configuration, can freely control the pulse width and duty ratio, and is inexpensive.

〔従来の技術〕[Conventional technology]

第2図は従来のパルス発生回路の一例を示す回路図、第
3図はパルス発生回路の動作を表すタイムチャートであ
る。
FIG. 2 is a circuit diagram showing an example of a conventional pulse generating circuit, and FIG. 3 is a time chart showing the operation of the pulse generating circuit.

第2図においてパルス幅とデユーティ比を制御できる従
来のパルス発生回路は、3個のNAND回路11.12
.13を用いたマルチバイブレークの、RC充放電回路
を構成する抵抗の一部に可変抵抗14を使用し、その両
側に2個のダイオード15.16を直列に接続すること
によって、コンデンサ17に充電する時とコンデンサ1
7が放電する時の時定数を変えている。
In Fig. 2, the conventional pulse generation circuit that can control the pulse width and duty ratio consists of three NAND circuits 11 and 12.
.. The capacitor 17 is charged by using a variable resistor 14 as a part of the resistor constituting the RC charging/discharging circuit of the multi-bye break using 13, and by connecting two diodes 15 and 16 in series on both sides of the variable resistor 14. time and capacitor 1
7 changes the time constant when discharging.

即ち分割された可変抵抗14の分抵抗をそれぞれ14a
、14bとすると、コンデンサ17に充電する時の時定
数は固定抵抗18と分抵抗14aの合計値で決まり、コ
ンデンサ17が放電する時の時定数は固定抵抗18と分
抵抗14bの合計値で決まる。
That is, the resistances of the divided variable resistors 14 are each 14a.
, 14b, the time constant when charging the capacitor 17 is determined by the total value of the fixed resistor 18 and the dividing resistor 14a, and the time constant when the capacitor 17 is discharging is determined by the total value of the fixed resistor 18 and the dividing resistor 14b. .

その結果先頭のNAND回路11の入力端子11aには
第3図に■で示す信号が入力され、NAND回路19の
出力端子19aには第3図に■で示すパルス信号が発生
する。
As a result, the input terminal 11a of the NAND circuit 11 at the top receives a signal indicated by ■ in FIG. 3, and the output terminal 19a of the NAND circuit 19 generates a pulse signal indicated by ■ in FIG.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

従来のパルス発生回路は上述の如く可変抵抗14の分抵
抗を変化させることにより、パルス信号のパルス幅とデ
ユーティ比を制御することができる。
The conventional pulse generating circuit can control the pulse width and duty ratio of the pulse signal by changing the resistance of the variable resistor 14 as described above.

しかし分抵抗14aと分抵抗14bの合計値は常に一定
であり、発生するパルス信号の幅T1とパルスの発生間
隔T2の合計Tが一定で、パルス幅とデユーティ比を別
個に制御することができないという問題があった。
However, the total value of the dividing resistor 14a and the dividing resistor 14b is always constant, and the sum T of the width T1 of the generated pulse signal and the pulse generation interval T2 is constant, and the pulse width and duty ratio cannot be controlled separately. There was a problem.

〔問題点を解決するための手段〕[Means for solving problems]

第1図は本発明になるパルス発生回路の一実施例を示す
回路図である。
FIG. 1 is a circuit diagram showing an embodiment of a pulse generating circuit according to the present invention.

上記問題点は直列に接続された少なくとも1個のNAN
D回路21と2個の反転回路22.23を有し、互いに
逆方向に電流の流れるダイオード24.25を介して、
2(11ilの可変抵抗26.27の一端を反転回路2
3の出力側にそれぞれ接続すると共に、可変抵抗26.
27の他端と反転回路23の入力側との間をコンデンサ
28を介して接続し、且つ可変抵抗26.27の他端と
NAND回路21の入力側との間を、抵抗29を介して
接続してなる本発明のパルス発生回路によって解決され
る。
The above problem is caused by at least one NAN connected in series.
It has a D circuit 21 and two inverting circuits 22 and 23, and through diodes 24 and 25 through which current flows in opposite directions,
2 (11il variable resistor 26, one end of 27 is connected to inverting circuit 2
3, and the variable resistors 26.
The other end of the variable resistor 26.27 and the input side of the inverting circuit 23 are connected via a capacitor 28, and the other end of the variable resistor 26.27 and the input side of the NAND circuit 21 are connected via a resistor 29. This problem is solved by the pulse generating circuit of the present invention.

〔作用〕[Effect]

第1図においてNAND回路21と2個の反転回路22
.23で構成された、マルチバイブレータに別個に操作
できる2個の可変抵抗を挿入し、コンデンサ28に充電
する時とコンデンサ28が放電する時の時定数を変える
ことによって、パルス幅とデユーティ比を自由に制御で
きる簡略化されたパルス発生回路を形成することができ
る。
In FIG. 1, a NAND circuit 21 and two inverting circuits 22
.. By inserting two variable resistors that can be operated separately into the multivibrator consisting of 23 and changing the time constants when charging the capacitor 28 and when discharging the capacitor 28, the pulse width and duty ratio can be freely controlled. It is possible to form a simplified pulse generation circuit that can be controlled precisely.

〔実施例〕〔Example〕

以下添付図により本発明の実施例について詳細に説明す
る。
Embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

第1図において本発明になるパルス発生回路は、直列に
接続された1個のNAND回路21と2個の反転回路2
2.23からなるマルチバイブレークの、RC充放電回
路を構成する抵抗として可変抵抗26.27を使用し、
互いに逆方向に電流の流れるダイオード24.25を介
して、2個の可変抵抗26.27の一端を反転回路23
の出力側にそれぞれ接続すると共に、コンデンサ28を
介して可変抵抗26.27の他端を反転回路23の入力
側に接続することによって、コンデンサ28に充電する
時とコンデンサ28が放電する時の、時定数が異なるR
C充放電回路を構成することができる。
In FIG. 1, the pulse generating circuit according to the present invention includes one NAND circuit 21 and two inverting circuits 2 connected in series.
Using a variable resistor 26.27 as a resistor that constitutes an RC charging/discharging circuit of a multi-bye break consisting of 2.23,
One end of the two variable resistors 26 and 27 is connected to the inverting circuit 23 through diodes 24 and 25 through which current flows in opposite directions.
By connecting the other ends of the variable resistors 26 and 27 to the input side of the inverting circuit 23 via the capacitor 28, when the capacitor 28 is charged and when the capacitor 28 is discharged, R with different time constants
A C charging/discharging circuit can be constructed.

即ちコンデンサ28に充電する時の時定数は可変抵抗2
6によって決まり、コンデンサ28が放電する時の時定
数は可変抵抗27によって決まる。その結果抵抗29を
介して可変抵抗26.27の他端と接続されている、N
AND回路21の入力端子21aに第3図に■で示す信
号が入力され、反転回路31の出力端子31aには第3
図に■で示すパルス信号が発生する。かかるパルス発生
回路は従来のパルス発生回路とは異なり、二つの可変抵
抗26.27をそれぞれ別個に操作できるため、発生す
るパルス信号の幅T1とパルスの発生間隔T2、即ちパ
ルス幅とデユーティ比との間に相関関係が無く、パルス
幅とデユーティ比を広い範囲にわたって自由に制御する
ことが可能になる。
In other words, the time constant when charging the capacitor 28 is the variable resistor 2.
6, and the time constant when the capacitor 28 discharges is determined by the variable resistor 27. As a result, N is connected via the resistor 29 to the other end of the variable resistor 26.
A signal indicated by ■ in FIG. 3 is input to the input terminal 21a of the AND circuit 21, and a third
A pulse signal indicated by ■ in the figure is generated. Unlike conventional pulse generating circuits, this pulse generating circuit can operate the two variable resistors 26 and 27 separately, so that the width T1 of the generated pulse signal and the pulse generation interval T2, that is, the pulse width and the duty ratio There is no correlation between the two, making it possible to freely control the pulse width and duty ratio over a wide range.

なおNAND回路21の他方の入力側と電源VDDとの
間に挿入されている反転回路32.33は、電源VDD
に含まれるノイズ等によってパルス信号が乱れるのを防
止する回路、また反転回路32の入力側に接続されてい
るスイッチ34は、パルス信号のレヘルGNDレベルに
固定するためのものである。
Note that the inverting circuits 32 and 33 inserted between the other input side of the NAND circuit 21 and the power supply VDD are connected to the power supply VDD.
A switch 34 connected to the input side of the inversion circuit 32 is used to fix the pulse signal at the level GND.

このようにNAND回路と2個の反転回路で構成された
、マルチバイブレークに別個に操作できる2個の可変抵
抗を挿入し、コンデンサに充電する時とコンデンサが放
電する時の時定数を変えることによって、パルス幅とデ
ユーティ比をそれぞれ独立させて自由に制御できる、簡
略化されたパルス発生回路を形成することができる。
In this way, by inserting two variable resistors that can be operated separately into the multi-by-break, which is composed of a NAND circuit and two inverting circuits, and changing the time constants when charging and discharging the capacitor. , it is possible to form a simplified pulse generation circuit in which the pulse width and duty ratio can be independently and freely controlled.

〔発明の効果〕〔Effect of the invention〕

上述の如く本発明によればパルス幅とデユーティ比をそ
れぞれ独立させて、自由に制御可能なパルス発生回路を
提供することができる。
As described above, according to the present invention, it is possible to provide a pulse generation circuit in which the pulse width and duty ratio can be controlled independently and freely.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明になるパルス発生回路の一実施例を示す
回路図、 第2図は従来のパルス発生回路の一例を示す回路図、 第3図はパルス発生回路の動作を表すタイムチーヤード
、 である。図において 21はNAND回路、 21aは入力端子、22.23
は反転回路、 24.25はダイオード、26.27は
可変抵抗、 28はコンデンサ、29は抵抗、    
 31.32.33は反転回路、31aは出力端子、 
 34はスイッチ、をそれぞれ表す。 本発明1;なるノでルス肩n回路の一実)セイッリをホ
■ロ路図第1 因 従来のパルス今生回路の一イ列を示τ巨■各凹第2図
Fig. 1 is a circuit diagram showing an embodiment of the pulse generation circuit according to the present invention, Fig. 2 is a circuit diagram showing an example of a conventional pulse generation circuit, and Fig. 3 is a time chart showing the operation of the pulse generation circuit. , is. In the figure, 21 is a NAND circuit, 21a is an input terminal, 22.23
is an inverting circuit, 24.25 is a diode, 26.27 is a variable resistor, 28 is a capacitor, 29 is a resistor,
31, 32, and 33 are inverting circuits, 31a is an output terminal,
34 represents a switch. Invention 1: The result of the n-circuit in the present invention) Figure 1 shows a row of the conventional pulse current circuit Figure 2

Claims (1)

【特許請求の範囲】[Claims] 直列に接続された少なくとも1個のNAND回路(21
)と2個の反転回路(22、23)を有し、互いに逆方
向に電流の流れるダイオード(24、25)を介して、
2個の可変抵抗(26、27)の一端を該反転回路(2
3)の出力側にそれぞれ接続すると共に、該可変抵抗(
26、27)の他端と該反転回路(23)の入力側との
間をコンデンサ(28)を介して接続し、且つ該可変抵
抗(26、27)の他端と該NAND回路(21)の入
力側との間を、抵抗(29)を介して接続してなること
を特徴とするパルス発生回路。
At least one NAND circuit (21
) and two inverting circuits (22, 23), through diodes (24, 25) through which current flows in opposite directions,
One end of the two variable resistors (26, 27) is connected to the inverting circuit (2
3), and the variable resistor (
The other ends of the variable resistors (26, 27) and the input side of the inverting circuit (23) are connected via a capacitor (28), and the other ends of the variable resistors (26, 27) and the NAND circuit (21) are connected to each other via a capacitor (28). A pulse generating circuit characterized in that the pulse generating circuit is connected to the input side of the circuit via a resistor (29).
JP62070717A 1987-03-25 1987-03-25 Pulse generation circuit Pending JPS63236406A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62070717A JPS63236406A (en) 1987-03-25 1987-03-25 Pulse generation circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62070717A JPS63236406A (en) 1987-03-25 1987-03-25 Pulse generation circuit

Publications (1)

Publication Number Publication Date
JPS63236406A true JPS63236406A (en) 1988-10-03

Family

ID=13439595

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62070717A Pending JPS63236406A (en) 1987-03-25 1987-03-25 Pulse generation circuit

Country Status (1)

Country Link
JP (1) JPS63236406A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0410709A (en) * 1990-04-27 1992-01-14 Casio Comput Co Ltd Astable multivibrator

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0410709A (en) * 1990-04-27 1992-01-14 Casio Comput Co Ltd Astable multivibrator

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