JPS6323652B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a pattern inspection device for inspecting defects in a pattern of a printed circuit board mask or a printed circuit board, etc., and particularly to a pattern inspection device for inspecting defects in a pattern using a special inspection algorithm. The present invention relates to a pattern inspection device for inspecting.

[Background technology]

The IC is equipped with a large number of integrated circuit (IC) elements.
For example, the printed circuit board that supports and connects the
As shown in Figure A, a large number of terminal conductor patterns (lands) 12 and a large number of conductor patterns (lands) 14 into which IC pins are inserted are provided around the board 10, and these are wires (leads). 1
6 and are appropriately connected. Although not shown, holes for inserting IC pins are formed in the conductive pattern 14. The conductor patterns 12, 14, 16 are made by a photo process as is well known. In other words, it is made by applying a photoresist to a printed circuit board with copper foil on its surface, exposing it with a mask, developing it, and then etching it. As shown, if possible, there may be a minute conductor pattern (black dot) 18 in a place other than the land 12, a partially missing part 20 of the lead 16 as shown in C of the same figure, or a whisker-like extension from the land 12 and the lead 16 (not shown). Small projections (beards) may be present.

There are various causes for these formations, one of which is defects existing in the mask itself.
Masks are generally made by projecting a black and white pattern (mask screen) drawn on paper by a designer on a scale onto a glass substrate coated with a photosensitizer, and then developing it. In addition, as the mask is repeatedly used, defects such as partial pattern omissions are introduced. Therefore, it is necessary to properly inspect the mask for defects at the time of manufacture and during use to check whether it is normal or not.

[Conventional technology and problems]

Conventionally, this mask inspection has relied on visual inspection, in which the presence or absence of pinholes, black spots, etc. is checked over the entire fine pattern on the substrate through a microscope, but this is a considerably troublesome task.

For this reason, devices for inspecting defects in such patterns have been developed and put into practical use. As shown in FIG. 2, such a conventional pattern inspection apparatus scans a laser beam from a laser light source 21 in the X direction of the figure using a scanning mirror 22, and the scanning beam passes through a scanner lens 23 and scans a pattern to be inspected such as a mask. The transmitted light is projected onto the object 30 to be inspected, and the transmitted light is transmitted to the photodetector 24.
and is converted into an electrical signal. Tested object 30
is mounted on a table (not shown), and the table is driven in the Y direction by a motor etc., so the scanning of the laser beam (X direction) and the movement of the table (Y direction)
A predetermined area of the object to be inspected 30 is optically scanned by the photodetector 24, and the pattern is converted into an electrical signal by the photodetector 24. This electrical signal (pattern signal) is input to the inspection circuit 40 and stored in the two-dimensional register, and then the signal at a predetermined bit position of the register is read out according to a predetermined inspection algorithm to detect defects. As shown in Fig. 3A, this inspection algorithm uses a plurality of linear bits in the 90° direction perpendicular to the pattern edge TEG formed in the 0° direction.
Sunspot detection pattern Pa consisting of S ₁ to S _o , K, and D
and the 3 bits GA1 to GA3, GB1 on both sides of the center
Consisting of a first guard pattern Pb consisting of ~GB3 and a second guard pattern Pc consisting of 1-bit GC and GD on both sides below it, in the scanning direction,
Arranged at 0°, 90°, 180°, and 270° directions. on the other hand,
In the 45°, 135°, 225 _° , and 315° directions, as _shown in FIG. 1 card pattern Pe (GA1~GA3, GB1~GB3)
, the second guard pattern Pf (GC, GD), and the third guard pattern Pg (GE1~GEn, GF1~
An inspection algorithm consisting of GFn) is arranged.

Among these, the black spot detection patterns Pa and Pd detect pattern edges and indicate the existence of the black spot part of the pattern and the length in the scanning direction, and the guard pattern prevents false detection at pattern bends near the detected pattern edges. , is for prohibiting detection of unspecified angular directions. For this reason, a normal test pattern is determined for each detection bit of the test pattern based on the following three detection conditions.

(1) The black spot detection patterns Pa and Pd detect pattern edges, that is, the contents of bits K and D are different, indicating the start of black spot detection, and the length of the black spot pattern in the scanning direction is indicated by the black spot detection.

(2) Each group of guard patterns Pb, Pe, and Pg shall contain one or more white bits.

(3) Guard patterns Pc and Pf must have the same sign,
In other words, when detecting the edge of the pattern to be tested, if there is a bend in the vicinity that may cause false detection, the guard pattern is used to prevent false detection.
This prohibits angles other than those specified.

In FIG. 4, the test patterns shown in FIGS. 3A and 3B are set in the two-dimensional shift register 401 of the detection circuit 40 in FIG. 2. In FIG. Normal pattern edge directions are 0°, 45°, 90°, 135°, 180°, 225°, 270°
゜、
Since the angle is limited to 8 directions of 315°, we can use the same pattern as in Figure 3 A at 0°, 90°, 180°, 270°, and the pattern in Figure 3 B.
By setting it to 45°, 135°, 225°, and 315°, it can be applied to all pattern edges.

In this way, defects such as black spots and whiskers can be detected, and by inverting the pattern signal stored in the two-dimensional register 401, chipping can also be detected.

It is said that this inspection mask can be applied to a pattern of the object to be inspected 30 whose angle is necessarily π/4×n, but cannot be applied to a pattern with other angles because there is a risk of over-detection.

On the other hand, in recent years, hexagonal land patterns have been used as land patterns for such printed boards, and in this case, the pattern angle is π/6×n (30°, 60°, . . . ).

For this reason, there was a problem that conventional pattern inspection equipment equipped with this inspection mask could not be used to inspect objects to be inspected with different pattern angles, and it was necessary to develop new inspection masks and inspection equipment. .

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a pattern inspection device that can use a pattern inspection device having an inspection mask created for a pattern at a specific angle to inspect objects to be inspected that have patterns at other angles. .

[Structure of the invention]

To achieve the above object, the present invention provides a register that stores an image pattern of an object to be inspected, and a defect inspection logic that inspects for defects by reading the logic of bits at a plurality of predetermined positions of the register according to a predetermined inspection mask. an error pattern memory for storing input data of the defect inspection logic circuit in response to a defect detected by the defect inspection logic circuit; and an error pattern inspection device for inspecting the contents of the error pattern memory. and a correction circuit that changes the input conditions of the defect inspection logic circuit, and when the correction circuit detects n or more identical data patterns from the error pattern memory, the correction circuit changes the input conditions and changes the input conditions of the inspection mask. It is characterized by correcting.

[Embodiments of the invention]

Hereinafter, the present invention will be explained in detail with reference to Examples.

FIG. 5 is a block diagram of an embodiment of the present invention.
In the figure, 401 is a two-dimensional memory, which is composed of a two-dimensional shift register as shown in FIG.
storing the serial pattern signal from the photodetector 24;
What is stored again as a two-dimensional pattern, 40
2 is a multiplexer, and a two-dimensional memory 401
A signal group at the bit position of the memory 401 to be extracted according to the inspection mask shown in FIG. It detects defects by taking the logic of the input signal group via the multiplexer 402 according to the defect detection logic, and is configured as shown in FIG. That is, FIG. 6 is a circuit diagram showing an example of the defect detection logic circuit 403,
This is a detection circuit that implements the detection logic explained in FIGS. 3A and 3B. In other words, D belonging to the black spot detection pattern Pa or Pd of the inspection pattern is directly written, and K is NOT
Detected via circuit 421, then guard pattern
Since Pc or Pf have the same sign under normal conditions, Gc and G _D
is input to the EXNOR circuit 422, and if it is normal, it becomes “1”
If it is abnormal, it becomes "0". Guard pattern Pb or Pe (G _A1 ~ _{G A3} ), Pb or Pe (G _B1 ~ _{G B3} ), Pg
(G _E1 ~ _{G Eo} ) and Pg (G _F1 ~ G _Fo ) contain one or more white bits during normal operation, so the NAND circuits 423 and 42
4,426,427, and if it is normal, it will be "1", and if it is abnormal, it will be "0". S ₁ to S _o of sunspot detection pattern Pa or Pd is OR because it is sunspot detection
It becomes the output of circuit 425.

Of the above logic circuits, if the logical product of the group A is taken, the detection condition of the inspection pattern of FIG.
If it is 8, it satisfies the detection conditions of the test pattern shown in Figure B, and if this result is "1", it is normal.
If it is "0", it is determined that it is defective. Furthermore, by logically ORing the outputs of each inspection pattern using an OR circuit, it can be determined that there is a defect in one or more of the eight directions.

Returning to FIG. 5, 404 is a defect pattern memory that stores the output of the multiplexer 402, that is, the input data of the defect detection logic circuit 403 every time the defect detection signal of the defect detection logic circuit 403 is output, and 405 is a comparison memory. 406 is a multiplexer control circuit that compares the contents of each data pattern in the defective pattern memory 404 and checks whether there are n identical data patterns. This is to control the multiplexer 402 when detecting the presence of a specific data pattern to prohibit the output of a specific signal of the input signal group so that n or more identical data patterns do not exist. Note that the comparator circuit 405 and the multiplexer control circuit 406 constitute a correction circuit.

Next, the operation of the embodiment shown in FIG. 5 will be explained. For normal pattern inspection, serial pattern signals from the photodetector 24 in FIG. 2 are input to the two-dimensional memory 401 and stored as a two-dimensional pattern. Assuming that all the gates of the multiplexer 402 are open and output of all input signals is permitted, the defect detection logic circuit 403 performs defect detection according to the defect detection logic shown in FIGS. 3A and 3B. . Since the two-dimensional memory 401 sequentially shifts the stored contents in accordance with the shift clock, the defect detection logic circuit 403 sequentially tests for defects using a group of input signals that change in synchronization with this shift.
All pattern signals in the dimensional memory 401 are inspected for defects. When the defect detection logic circuit 403 detects a defect, it outputs a defect detection signal. This defect detection signal is used to mark the corresponding address position on the drawing in an output device (not shown), thereby clearly indicating the defect position to a human being. Along with this, the defect pattern memory 40 uses the defect detection signal as the timing to capture the defect detection signal.
4 takes in the contents of the input signal (ie, input data) of the defect detection logic circuit 403 at this time and sequentially stores them. When one inspection is completed in this manner, that is, when the shift of the two-dimensional memory 401 is completed, the comparison circuit 405 inspects the contents of the defective pattern memory 404. That is, the comparison circuit 405 compares the contents of the defective pattern memory 404 and determines whether or not there are n or more identical data patterns. The reason for detecting the existence of identical data patterns here is that
In the case of defects, based on the premise that there are few defects with the same characteristics in a single film or substrate (i.e. the object to be inspected),
Defects with more than 1,000 defects are determined to be due to overdetection. Comparison circuit 405 compares the same data pattern with n
If the defect detection logic does not detect more than 1, the multiplexer control circuit 4
Control of 06 is not permitted. Conversely, when the comparison circuit 405 detects n or more identical data patterns, it notifies the multiplexer control circuit 406, and the multiplexer control circuit 406 inhibits part of the output of the multiplexer 402 to prevent over-detection. For example, since the input line that is likely to cause over-detection is known in advance from experience, the sunspot detection pattern Pa
Or control to reduce the number of bits of Pd,
In order to reduce the number of bits in each guard pattern,
The multiplexer control circuit 406 inhibits each gate of the multiplexer 402. After correcting the defect inspection logic (that is, the inspection mask) in this way, the two-dimensional memory 401 is shifted again in the same manner as described above, the defect detection logic circuit 403 performs defect detection, and the defect detection signal is used to detect the defect pattern. The input data is stored in the memory 404. After completing one inspection in this manner, the comparison circuit 405 again compares the contents of the defective pattern memory 404 and detects the presence of the same data pattern. Here, when the comparison circuit 405 does not detect n or more identical data patterns, the multiplexer control circuit 405 determines that there is no over-detection in the modified defect inspection logic.
control is not permitted, and the modification work for the inspection mask is terminated. Conversely, when the comparison circuit 405 detects n or more of the same data pattern again, it notifies the multiplexer control circuit 406, and the multiplexer control circuit 406 inhibits each gate of the multiplexer 402 so as to provide a different defect inspection logic. Then, the same inspection is performed again, further comparisons and judgments are made, and the defect inspection logic is corrected, and the process is repeated until finally there are no more than n identical defect data patterns in the defect pattern memory 404. In this way, the control pattern of the multiplexer 402 when there are no more than n identical data patterns in the defect pattern memory 404 is applied to the new defect inspection logic for defect inspection of the object to be inspected. Each time the pattern of the object to be inspected is changed, a modification request is issued from the outside, and the search for the optimum defect inspection logic is started.

In the above description, the multiplexer 402 is used for operation under optimal input conditions, but it may also be a simple group of gates, and if the pattern of the object to be inspected is limited in advance, the multiplexer control circuit 406 may be used. A control pattern optimal for that pattern may be stored in advance, and the multiplexer may be controlled using this control pattern.

Although the present invention has been described above using one embodiment, the present invention can be modified in various ways according to the gist of the present invention, and these are not excluded from the present invention.

〔Effect of the invention〕

As explained above, according to the present invention, there is a register that stores an image pattern of an object to be inspected, and a defect inspection logic that inspects for defects by taking the logic of bits at a plurality of predetermined positions of the register according to a predetermined inspection mask. an error pattern memory for storing input data of the defect inspection logic circuit in response to a defect detected by the defect inspection logic circuit; and an error pattern inspection device for inspecting the contents of the error pattern memory. and a correction circuit that changes the input conditions of the defect inspection logic circuit, and when the correction circuit detects n or more identical data patterns from the error pattern memory, the correction circuit changes the input conditions and changes the input conditions of the inspection mask. This feature has the effect that the inspection mask (defect detection logic) of a specific object to be inspected can be modified to the inspection mask of another object to be inspected, and therefore new inspection masks and equipment can be used. There is no need to create a pattern, and pattern inspection of various objects to be inspected can be performed using the same device.
Moreover, since the correction is automatically performed based on the input data in which a defect has been detected, the correction can be easily performed without any human intervention, and is extremely useful in practice.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the pattern configuration of a printed circuit board that is the object of the present invention, FIG. 2 is a diagram showing the configuration of a pattern inspection apparatus according to a conventional configuration, FIG. 5 is a block diagram of an embodiment of the present invention, and FIG. 6 is a circuit diagram of a main part of the structure shown in FIG. 5. In the figure, 30... object to be inspected, 401... two-dimensional memory, 402... multiplexer, 403... defect detection logic circuit, 404... defect pattern memory, 405... comparison circuit, 406... multiplexer control circuit.

Claims (1)

[Claims] 1. In a pattern inspection device that has a register that stores an image pattern of an object to be inspected and a defect inspection logic circuit that inspects for defects by reading the logic of bits at a plurality of predetermined positions of the register according to a predetermined inspection mask, an error pattern memory for storing input data of the defect inspection logic circuit in response to a defect being detected by the inspection logic circuit; and an error pattern memory for storing input data of the defect inspection logic circuit, and changing input conditions of the defect inspection logic circuit by inspecting the contents of the error pattern memory. A pattern inspection apparatus comprising: a correction circuit that corrects the inspection mask by changing the input condition in response to detecting a plurality of identical data patterns from the error pattern memory.