JPS6323664B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a novel structure of an insulated gate electrostatic induction transistor that has a sufficiently small gate capacitance, a low resistance during conduction, and exhibits unsaturated current-voltage characteristics.

Traditional field effect transistors are junction type,
All MOS types exhibit saturated current-voltage characteristics in which the drain current gradually saturates as the drain voltage increases.

On the other hand, a static induction field effect transistor (hereinafter referred to as SIT) in which the drain current continues to increase as the drain voltage increases, was proposed by one of the inventors of the present invention in Japanese Patent Publication No. 52-6076 "Field Effect Transistor" and Japanese Patent Publication No. 52-17720. It was proposed in "Field Effect Transistor".

SIT is superior in terms of high power, high withstand voltage, large current, low distortion, low noise, low power consumption, and high speed operation, and is superior to conventional bipolar transistors and field effect transistors, including its temperature characteristics. This is a transistor that has many advantages over other transistors. Its excellence has already been demonstrated both as an individual element and as an element for integrated circuits, and it is opening up new fields of application in various fields. Due to its high input impedance, the power required for driving is small, and it can be directly connected to the next stage, allowing for high integration.
It exhibits unsaturated current/voltage characteristics, large conversion conductance, and small output impedance, making it extremely suitable for integrated circuits that can accommodate a large number of fan outs.

The basic structure of MOS and MIS static induction transistors that operate in enhancement mode (E mode) or enhancement mode and depletion mode (D mode) was developed by the inventor of the present invention in Japanese Patent Publication No. 58-
No. 56270 “Insulated gate electrostatic induction field effect transistor and integrated circuit device” and Special Publication No. 1987-37799
No. ``Semiconductor Integrated Circuits'' and Japanese Patent Publication No. 60-44833 ``Insulated Gate Type Static Induction Transistor''.

Naturally, in order to reduce the gate capacitance of insulated gate transistors such as MOS and MIS SIT that exhibit unsaturated current-voltage characteristics,
Either the area of the gate electrode existing on the channel is reduced, or the thickness of the insulating layer under the gate electrode is increased. If the insulating film is made thicker, the voltage applied to the gate (threshold voltage) necessary to create an inversion layer and make the channel conductive increases, and much of the gate voltage is applied to the insulating film, which is undesirable in terms of operating characteristics. That's not the point. The remaining method is
All that is required is to make the gate electrode smaller. FIG. 1 shows a cross-sectional view of an n-channel type structure with a sufficiently small gate capacitance.

The high resistance regions 53', 63', 73' inserted on the side of the n ⁺ drain regions 54, 64, 74 almost become depletion layers due to the difference in diffusion potential with the opposite conductivity type regions 52, 62, 72 which become channels. The impurity density and its length are selected as follows. The insulating layers 55, 65, 75 made of SiO ₂ , Si ₃ N ₄ , Al ₂ O ₃ or a combination thereof on the channel region are set thin, and gate electrodes 56 , 66 , 76 are provided. The thickness of the insulating layer is from 100 Å to several 1000 Å.
In FIGS. 1c and 1e, the distance is set so that the drain region and the p-region substrate also form a depletion layer in the main operating region. The height of the potential barrier created by the opposite conductivity type region in front of the source is controlled by the gate voltage and drain voltage via the insulating layer. The length and impurity density of the channel region are such that as the drain voltage increases, the depletion layer region extends into the channel region and acts to lower the potential barrier in front of the source. That is, the depletion layer extends from the drain side to the source side so that the potential barrier to electrons created at the n ⁺ p junction can be controlled by the drain voltage. In extreme cases, the depletion layer from the drain side may completely reach the source region, and the potential barrier in front of the source may almost disappear. It is also possible to create a distribution in the impurity density in the channel region such that the density decreases toward the drain, or to move the specific gate position where the potential barrier is closer to the front of the source to sufficiently reduce the series resistance from the source to the specific gate. Makes the rise of the current noticeable.

Insulated gate transistors exhibiting unsaturated current-voltage characteristics, such as MOS and MIS SIT having the structure shown in FIG. 1, have a characteristic that the drain current rises quickly with respect to the drain voltage. Since the gate electrode is provided only on the required channel and the area is small, the capacitance between the gate and the substrate and the capacitance between the gate and the drain are extremely small, making it extremely suitable for high-speed operation. Furthermore, since the gate capacitance becomes very small, the power required for driving becomes small, and the number of fan-outs that can be obtained from an inverter, logic gate, clock pulse generator, etc. having the same driving capability increases. In addition, if the voltage applied to the gate electrode is applied mostly to the semiconductor in the channel area by thinning the insulating layer under the gate electrode or increasing its dielectric constant, the amount of carriers injected from the source to the drain side can be reduced. The control by the gate voltage is similar to that of a bipolar transistor, and the flow of carriers passing through the potential barrier in the channel section to the drain is exactly the same as that of a bipolar transistor.
The conversion conductance of insulated gate transistors, such as MOS and MIS SIT, which exhibit unsaturated current-voltage characteristics, is close to that of bipolar transistors and can be made to an extremely large value, and their output impedance is small, allowing for a large number of fan-outs. can do. However, traditional MOS,
In MIS SIT, the channel region is not limited to the vicinity of the gate (5 in Figure 1).
2, 62, 72, etc.), some of the carriers injected from the source into the channel are not controlled by the gate voltage, and the conversion conductance (Gm =
2I _D /2V _G ) is not maximized.

That is, carriers are injected into the channel region not only from the vicinity of the gate but also from the bottom of the source region, etc., and these carriers are not controlled by the gate voltage, resulting in a decrease in Gm.

An object of the present invention is to provide a novel structure of an insulated gate transistor that compensates for the above-mentioned drawbacks and exhibits unsaturated current-voltage characteristics with small gate capacitance and drain capacitance and large conversion conductance.

First, the potential of the MOS structure consisting of metal 113 - insulating layer 112 - semiconductor 111 as shown in FIG.
Let's briefly discuss electric field distribution. insulation layer thickness
l ₂ , dielectric constant ε ₂ , semiconductor impurity density N _D , dielectric constant ε ₁
shall be. The spatial coordinate x is taken from the boundary between the insulating layer and the semiconductor toward the semiconductor. Metals, including diffusion potential.
Reverse bias applied between semiconductors (semiconductor 111 is n
(negative voltage in this example) is V _a , the voltage applied to the insulating layer V ₀ , the electric field E ₀ , and the electric field E in the semiconductor
(x), potential V(x), and depletion layer width W, the respective values are shown in Chapter 4 of "Semiconductor Research (Volume 13)" published by Kogyo Research Association Co., Ltd. on July 10, 1978. As clarified on pages 93 to 95 of “Tannet”, is given by However, Wa ² =2ε ₁ V _a / _ND e, -e is a unit charge.

Let's say that the insulating layer is a SiO ₂ film with a thickness of 500 Å. N _D 1×10 ¹⁵ cm ^-3 or less, 1V or more
A voltage of 80% or more with respect to Va is applied to the semiconductor,
Controls the potential distribution within a semiconductor. Naturally, the smaller N _D is, the higher the proportion of voltage applied to the semiconductor portion is, and the more internal potential can be controlled. For example, if the thickness of the insulating layer is 500 Å SiO ₂ , the depletion layer when Va = 1V is N _D = 1×
For 10 ¹³ cm ^-3 , 1×10 ¹⁴ cm ^-3 , 1×10 ¹⁵ cm ^-3 ,
They reach depths of approximately 11 μm, 3.5 μm, and 1 μm, respectively.

Of course, if the reverse bias applied to the gate becomes large and an inversion layer is generated on the semiconductor surface and holes are present, the depletion layer width W becomes smaller than the value of the above-mentioned formula. Since the gate cannot control the current beyond the reach of the depletion layer from the surface, in order to increase the conversion conductance Gm, the current flow must be limited to the range from the gate to the depletion layer. That is, the thickness of the channel region must be within the range covered by the gate voltage. For example, as is clear from the above explanation, the impurity density in the channel region is N _D =1×
For 10 ¹³ cm ^-3 , 1×10 ¹⁴ cm ^-3 , 1×10 ¹⁵ cm ^-3 ,
At least the thickness near the source in the channel region
This means that Gm can be increased by making it thinner than 11 μm, 3.5 μm, or 1 μm. In order to achieve this, the height of the barrier against carriers from the source is lowered only in the vicinity of the gate, and that area is used as a channel region. That is, the source
If it is an n ⁺ region, the barrier height at the n ⁺ p ^- junction is lower than that at the n ⁺ p junction, so only the n ⁺ p ^- junction is formed under the gate, and the region below the source is n ⁺ p.
And it is sufficient. In this case, since the n ⁺ p ^-junction and the n ⁺ p junction are arranged in parallel, more carriers will flow toward the n ⁺ p ^- junction. And this p ^-
If the thickness of the channel region of the region is set to the thickness described above, carriers injected from the source can be efficiently controlled by the gate voltage, and Gm can be increased. A specific example of a MOS-SIT configured to increase Gm in this way will be explained using FIG. 3, taking an n-channel case as an example.

n ⁺ regions 121 and 123 are source and drain regions, p ^- region 122 is a channel region, p
Region 125 is the substrate, 121' and 123' are the source.
The drain electrode 124 is a gate electrode. 1
Reference numeral 26 denotes an insulating layer, which is made thin under the gate electrode. The impurity density of each region is 12
1,123:10 ¹⁷ ~10 ²¹ cm ^-3 , 122:10 ¹³ ~10 ¹⁶
cm ^-3 , 125: about 10 ¹⁵ to 10 ¹⁸ cm ^-3 . M.O.S.
Insulated gate transistors exhibiting unsaturated current-voltage characteristics such as SIT are devices in which majority carriers in the source region are directly injected into the drain-side depletion layer, so the higher the density of the source region, the better.
The thickness of the insulating layer under the gate electrode is made thin and is set to a desired value in the range of 100 Å to several thousand Å. The impurity density in the region 122 is such that when a predetermined drain voltage is applied, a depletion layer easily extends from the drain side and reaches the vicinity of the source or inside the source region, controlling the potential barrier caused by the n ⁺ p junction near the source. The value has been selected. As described above, this potential barrier is controlled by the gate. Since the potential barrier height is lowered by increasing the drain voltage, the amount of electrons injected from the source side to the drain side across this lowered barrier increases. Since the amount of electrons crossing the barrier is governed approximately exponentially, at low currents the current increases according to an exponential law with respect to both the gate voltage and the drain voltage.
As the drain current increases, the negative feedback effect due to the series resistance from the source to the potential barrier becomes significant, and the current-voltage characteristics deviate from the exponential law. Of course, the space charge effect in the drain-side depletion layer also comes into play when the drain current becomes very large. When the positive voltage on the gate is made deep enough to form an inversion layer on the surface, the current flowing resistively will also be included in the drain current. Figure 3a shows the source
This is an example where the drain is made in the p ^-region . FIG. 3b shows a structure for preventing punch-through or punch-through current from flowing between the sources and drains of adjacent insulated gate transistors as the degree of integration increases. There is a high resistance p ^- region around the channel and drain. The reason why the drain is surrounded by a p ^- region is to reduce the drain capacitance. The substrate is often kept at the same potential as the source. Then, in the cases shown in FIGS. 3a and 3b, electrons flow only in the vicinity of the surface away from the substrate. In the case of surface conduction, mobility is low and resistance tends to be high. Electrons injected from the source side are
If the flow spreads away from the surface, the mobility will be higher and the resistance will be lower. An example of achieving this is shown in Figure 3c. That is, as you go towards the drain side, the p ^- region becomes wider and the p region 1
25 has a structure in which it is not in contact with the drain region. In such a structure, not only resistance is reduced, but drain capacitance is also reduced, making high-speed operation even more pronounced. However, the conventional MOS-SIT shown in the examples shown in FIGS. 3a to 3c had the disadvantage that the source capacitance was large because the source was in contact with the p-region having a high impurity density.

Another drawback was that punching-through current easily flows between the sources and drains of adjacent SITs.
SUMMARY OF THE INVENTION An object of the present invention is to provide a further improved structure to overcome the above-mentioned drawbacks of conventional MOS-SIT.

The insulated gate static induction transistor of the present invention will be explained in detail below.

FIG. 4 shows a sectional view of a specific example of the insulated gate type static induction transistor of the present invention. n ⁺ area 121,
123 is a source and drain region, p region 122 is a region that becomes a channel, p region 122' has a higher impurity density than p region 122, but p ⁺ substrate 12
A region with lower impurity density than 5', n ^- region 12
2'' is a high resistance layer inserted on the drain side.
Reference numerals 121', 124, and 123' are a source electrode, a gate electrode, and a drain electrode, respectively. Reference numeral 126 is an insulating layer, which is formed thinly below the gate electrode. The impurity density of each region is 121 and 123, respectively:
10 ¹⁷ ~ 10 ²¹ cm ^-3 , 122: 10 ¹⁴ ~ 10 ¹⁶ cm ^-3 , 12
2': 10 ¹⁵ ~ 10 ¹⁸ cm ^-3 , 122'': 10 ¹² ~ 10 ¹⁵ cm ^-3 ,
125': about 10 ¹⁷ to 10 ²⁰ cm ^-3 . In the example of FIG. 4, the source region 121 is a p ^- region 1 with high impurity density.
Since it is not in direct contact with 25' and is in contact with p-region 122', which has a lower impurity density than 125', the source capacitance is also smaller than in the conventional MOS-SIT shown in Figures 3a to 3c. There is. A high-resistance region of the same conductivity type as the drain, that is, an auxiliary drain region, is provided on the drain side, and the drain capacitance is small, and electrons injected from the source side can be absorbed because there is no gate electrode above the n ^- region. , it spreads and flows quite far from the surface. The p-region that becomes the channel is provided only near the source,
The impurity density is higher than those in FIGS. 3a to 3c. When a voltage is applied to the drain, a depletion layer extends in the p region and reaches the vicinity of the source or into the source region. This structure has a small resistance, allows current to flow easily, and has a small drain capacitance and gate capacitance, which, together with a large conversion conductance, makes it suitable for high-speed operation. Needless to say, the depth at which carriers flow near the source in FIG. 3 is set within the range that is affected by the gate voltage. Since the gate electrode is provided only near the source in order to conduct the injected carriers away from the surface, the surface potential is lowered by the gate electrode on the side near the drain region, and carriers flow through that part. disappears, and the carrier expands and flows inside the crystal. Adjacent SITs
The punch-through or punch-through current between the source and drain of the transistor is extremely small due to the effect of the relatively high impurity density p region 122'.

When a gate voltage is applied in the direction in which an inversion layer is generated in an insulated gate transistor exhibiting unsaturated current-voltage characteristics such as MOS or MIS SIT of the present invention,
Although carrier injection occurs violently even on the surface,
Since the channel is made of a relatively high resistance region, the space charge effect of the injected carriers substantially widens the channel width, covering a large area.
Carrier is effectively injected.

The fact that the insulated gate transistors of the present invention, such as MOS and MIS SIT, exhibiting unsaturated current-voltage characteristics can be applied to integrated circuits (logic and memory) is described in Japanese Patent Publication No. 60-44833, "Insulated Gate Static Induction As stated in "Transistor". NOR gates, NAND gates, complementary circuits, etc. can all be configured. The circuit configuration at the time of construction is described therein.

For example, regarding complementary circuits,
Figure 7 of No. 44833, Statistic of complementary configuration
The RAM is shown in FIG. Similarly,
Examples of NAND gates are Figure 8b, Figure 9b, NOR
Examples of gates are shown in Figures 8a and 9b. In either circuit configuration, the characteristics of the insulated gate transistor of the present invention, which has a small gate capacitance, a large conversion conductance, and a small output impedance when conducting, are fully utilized, allowing extremely high-speed operation. It turns out.

The structure of an insulated gate transistor exhibiting unsaturated current-voltage characteristics such as MOS or MIS SIT according to the present invention is not limited to the embodiment shown in FIG. 4. The conductivity type may be reversed, or
The shape of the pp ^- boundary is not limited to these shapes either. In short, in the channel from the source to the drain, a potential barrier occurs in front of or near the source in the main operating state, and the height of the potential barrier is effectively controlled by the gate voltage and drain voltage. Any structure that causes almost no damage to the surface may be used. For example, it may be constructed along the surface of a semiconductor substrate provided with a V-shaped or U-shaped cut region. When a gate is provided along a region cut into a V-shape or a U-shape in this way, the source region and drain region are formed on the same main surface of the semiconductor substrate as shown in FIGS. 3 and 4. cannot be set in Either region is provided on the opposite main surface or is formed as a buried region in the substrate. In FIG. 4, the impurity density of the p ^- region 122 constituting the channel is configured to increase from the drain to the source, so a potential barrier is created in front of or near the source, and its peak becomes sharp. It is valid. If the impurity density of the p ⁺ region 125' is configured to increase from the drain to the source, the effect will be further enhanced.

The insulated gate transistors that exhibit unsaturated current-voltage characteristics, such as MOS and MIS SIT mentioned above, are
All of these can be manufactured by conventionally known crystal techniques, diffusion techniques, ion implantation techniques, microfabrication techniques, selective diffusion, selective etching, selective growth, selective oxidation, and the like.

Insulated gate transistors such as MOS and MIS SIT of the present invention exhibiting unsaturated current-voltage characteristics have a structure in which a potential barrier (specific gate) occurs in the region near the source that should become a channel in the main operating state. The region from the intrinsic gate to the drain is a high resistance region and a depletion layer, and the carrier drifts. The channel portion has dimensions and impurity density such that potential control by the gate is effective. In particular, in the present invention, a peripheral region is provided below the channel region and the source region, which has the same conductivity type as the channel region and has a higher impurity density than the channel region.
Gm was further increased compared to MOS-SIT.
Furthermore, at least in a part of the channel region,
Gm can also be increased by adjusting the impurity density and dimensions so that the channel region is depleted in the thickness direction by the gate voltage applied to the gate. With this configuration, the gate capacitance can be made sufficiently small, the source-to-substrate capacitance and the drain-to-substrate capacitance can be made sufficiently small, a sufficiently large current can be generated with a small drain voltage, and the conversion conductance can be increased. Due to its low output impedance, it operates at extremely low power and high speed. Furthermore, since the electrons injected from the source travel in the bulk away from the surface, they have high mobility and operate at extremely high speeds. Furthermore, when integrated, the punch-through current between the sources and drains of adjacent transistors is also small. Coupled with the fact that its manufacturing is not too complicated,
When applied to logic circuits and storage devices, it brings about extremely significant performance improvements, and its industrial value is extremely large.

[Brief explanation of drawings]

Figures 1a to 1e are cross-sectional views of examples of conventional MOS and MIS SITs, Figure 2 is a diagram showing the MIS structure, and Figure 3 is a cross-sectional view of an example of a conventional MOS and MIS SIT.
Figures a, b, and c show examples of conventional insulated gate transistors, and FIG. 4 shows an embodiment of the insulated gate transistor of the present invention.

Claims (1)

[Claims] 1. First conductivity type high impurity density semiconductor substrate 125'
and a second conductivity type low impurity density first semiconductor region 12 formed in a part of the upper part of the semiconductor substrate.
2'', a second semiconductor region 122' of a first conductivity type having a lower impurity density than the substrate and formed on the top of the semiconductor substrate so as to surround the first semiconductor region; A third semiconductor region of a second conductivity type with a high impurity density is formed in a part of the upper part of the first semiconductor region.
a second conductivity type high impurity density fourth semiconductor region 121 formed in a part of the upper part of the second semiconductor region; a fifth semiconductor region 122 of a first conductivity type having a lower impurity density than the second semiconductor region formed in the second semiconductor region; and a gate insulating film formed on a part of the surface of the fifth semiconductor region;
A gate electrode 124 formed on the top of the gate insulating film, a source electrode 121' formed on the top of the fourth semiconductor region, and a drain electrode 123' formed on the top of the third semiconductor region. the fourth semiconductor region is a source region;
The third semiconductor region is a drain region, and the fifth semiconductor region is a drain region.
The portion of the semiconductor region facing the drain region is defined as a channel region, and the height of the potential barrier formed near the source region of the channel region is determined by the gate voltage applied to the gate electrode and the voltage applied to the drain electrode. An insulated gate transistor characterized by being controlled by both drain voltage and exhibiting unsaturated current-voltage characteristics shown by an exponential law. 2. The insulated gate transistor according to claim 1, wherein the impurity density of the channel region increases from the drain region toward the source region.