JPS63242564A - Printer signal processing circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a video printer that receives video signals as input, and particularly to a printer signal processing circuit suitable for high-speed printing.

[Conventional technology]

The conventional apparatus has a structure in which data is read out from an image memory and printed every 1 line, as described in Japanese Patent Application Laid-Open No. 58-138667. However, the printing speed of one line is one frame period or slower, and no consideration has been given to application to high-speed printing and data reading and writing.

[Problem that the invention seeks to solve]

The above conventional technology does not take into consideration data reading, writing, and high-speed printing, including data processing functions.
There was a problem in that high-speed printing was not possible because no consideration was given to the system configuration and tireing control so that one line of printing would be shorter than one frame period.

An object of the present invention is to provide a signal processing circuit for a printer that is capable of high-speed printing.

[Means for solving problems]

The above purpose is to write to the memory field by field, switch the read operation, divide the field into a write-only slot and a read-only slot, provide a data latch circuit on the read side or the write side, and write the memory at the same timing. This is achieved by eliminating access to

[Effect]

Memory is divided by addresses (divided into several areas,
When a field unit area is used for writing, other areas are used for reading. Furthermore, by switching between writing and reading operations at regular intervals within each field, and by providing a data latch circuit on the reading or writing side,
Duplication of memory areas and duplication of writing and reading at the same timing during high-speed printing operations can be avoided.

〔Example〕

An embodiment of the present invention will be described below with reference to FIG.

Figure 1 shows the signals of a video printer that samples video in the vertical direction, stores it in memory, performs certain processing, and then sends this data to a thermal head, which generates heat according to the signal level and prints one line. It is a processing circuit. In Figure 1, 1 is the input video signal A
An AD converter that performs D conversion, 2 a latch circuit that temporarily stores the AD converted data, 3 a memory that stores the number of AD converted data, 4 a write pulse generation circuit that controls writing, and 5 a composite circuit. A synchronization separation circuit separates a vertical synchronization signal and a horizontal synchronization signal from a synchronization signal. 6 is a write lower address circuit that generates a lower part of a write address. 7 receives a print command and generates a lower part of a read address. 1ead lower address circuit,
9 is a memory area selection circuit that determines the upper address of the memory and determines the area to be used in the memory; 10 is a switching circuit that switches between a write address and a read address using a slot signal; and 11 is a latch that latches data read from memory 3. The circuit 12 is a halftone control circuit for driving a thermal head, and the numeral 13 is a thermal head consisting of, for example, 512 columns. This thermal head 13 has 512 shift registers 13α and 512 latch circuits 13A.
and 512 gate circuits 13C and 512 heating elements 13
It consists of I:L.

In addition, Figs. 2 and 3 show the vIylC period, respectively.

It is a time chart showing operation in a 1Jzync cycle.

FIG. 4 shows a memory map that stores 512 lines. This will be explained below using the diagram.

First, as shown in Figure 4, the memory is divided into four areas A, B, C, and D each with 512 lines, and each area receives 512 lines of data in frame units as shown in Figure 2. The line printing mode will be explained. Memory areas A and B take in data for two lines in one frame period. The captured data is read out in the order of memory areas A and H in the next frame to print two lines. At this time, two lines of data are written into memory areas C and D. Thereafter, the printing operation is performed one line at a time in each field by switching sequentially. An example of a circuit that performs such an operation is shown in FIG.

The primary color signal or monochrome signal input to the AD is once stored in the latch circuit 2 after AD conversion.

Here, as shown in FIG. 3, the AD conversion clock samples the first part ADCKI of the video signal at the left end of the print, and the last part AT)CK2 of the video signal at the right end. Further, at this time, in order to write two lines in areas of memories A, B or C, D, sampling is performed twice in succession. The data captured in this manner is written to the memory 3 during the two slot period immediately after Hzync. At this time, the write pulse generation circuit 4 generates a clock for controlling the address circuit 6 and the memory 3 based on the synchronously separated V and Hzync, and switches the switching circuit 10 to the write side only during this period.

On the other hand, when reading, the print command is read out and the counter 7
When it receives the message, it counts up the 111th address and reads out memory 3 using something other than writegtlot.

The data thus read out is once latched by the latch circuit 11 and then input to the head 13 via the halftone control circuit 12. In the head, after 512 lines of data are input to the shift register 13a, this data is latched to the latch 13h, and then sent to the gate 13 by the halftone control circuit 12.
Close C and turn on only the necessary lines to generate heat. This is controlled ON-OFF according to the level of each line to obtain a print for one line with gradations. By sequentially performing this process line by line, a print image is obtained.

As explained above, in the present invention, high-speed printing is achieved by alternately switching memory areas and printing one line at a time, with two frames as one cycle.

Also, at this time, the writing and reading slots are divided to avoid timing overlap due to high-speed printing.

In this embodiment, printing of 1 line/1 field has been explained, but for faster printing operation of 70.5 fields per line, the memory area is divided into 8 areas and 4 areas are written in 1 frame period. , the remaining four lines can be controlled by printing and reading.

Furthermore, in order to reduce the usage amount of the memory 3, field operations can be performed by controlling the upper bits of the memory area selection circuit 9.

As shown in Figure 2, this involves sampling only 256 lines of odd or even fields, and then sampling the remaining 256 lines.
It replaces a line with the data of the previous line. Such control only needs to control the memory area, and the memory can be reduced with a simpler operation.

FIG. 5 shows another embodiment according to the present invention. In FIG. 5, the same symbols as in FIG. 1 have the same functions. 20 is a dual port memory 20 that can transfer column data to the shift register 20b at once. 21 is an Ex-OR circuit between the output of the shift register 13α of the head 13 and the shift register in the memory. 22 is an I10 control circuit that generates a write pulse. This will be explained below using the drawings.

It is known that the dual port memory 20, which can transfer column data in parallel to the shift register 20b, has an access speed that is about 10 times faster using the shift register 206 than conventional random access in which an address is determined and read. ing. Therefore, when writing, conventional random access is used, and when reading, serial access using the shift register 20h is performed to increase the speed.

The operation will be explained below according to the diagram. The video signal is once A
After D conversion, it is taken into the latch circuit 2.

Here, write the AD converted data to memory,
If the halftone control circuit 12 converts the data into 0N-OFF data during reading, high-speed printing is not possible if the speed of the halftone control circuit is slow.
This section explains how to write to . In this way, there is nothing other than the shift register 20b in the memory or the shift register 13a in the head that limits the speed at the time of reading, that is, at the time of printing, and it becomes possible to cope with higher-speed printing. FIG. 6 shows this situation. Only the position corresponding to the input level as shown in the figure 1
and records 0 in all remaining fields. At the time of reading, the shift register 13α in the head is first
By writing all 1's in , and passing the output of the shift register 20b from the memory 20 and the Ex-OR circuit 21, the shift register 13α is set to ON and OFF.
Data is obtained. Therefore, the in-head shift register 13α is preset by the print command. On the other hand, memory 20 needs to be written with 0 first. For this reason I
10 control circuit to set it to 10ft o and bring it to the initial state. After that, write 1 to the memory address corresponding to the input level. In this way, the serial access port is used when writing to and reading from the memory 20, and the memory area is further divided into 4 or 8 for control, thereby making it possible to print at a higher speed.

〔Effect of the invention〕

According to the present invention, it is possible to read one line of data at a higher speed, so there is an effect that printing can be done in a shorter time.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram of an embodiment of the present invention, and FIG. FIG. 3 is a timing chart showing the operation, FIG. 4 is a memory map showing memory areas, FIG. 5 is a block diagram of another embodiment of the present invention, and FIG. 6 is a memory map of the same. l...AD, 12...halftone control circuit, 2...latch, 13...head, 3...memory, 20...memory, 6...
...Wr * tg lower address, 7...R#αd
Lower address. , Katsuo Ogawa, patent attorney. Δforce P effect tone 6 Figure (b) Eight power P all W same

Claims (1)

[Claims] 1. A memory that records line data to be printed, a halftone control circuit that receives data read from the memory, a shift register that receives on/off data from the halftone control circuit, and a shift register connected in parallel. In a video printer configured with a thermal head consisting of a latch circuit, a gate circuit for the output of the latch circuit, and a heating element connected to the gate output, a memory area selection circuit inputs a vertical synchronization signal and generates an upper address of the memory. 1. A printer signal processing circuit comprising: and a switching circuit for switching write and read lower addresses.