JPS6324638A - Microscopic hole filling method - Google Patents

Microscopic hole filling method

Info

Publication number
JPS6324638A
JPS6324638A JP16665286A JP16665286A JPS6324638A JP S6324638 A JPS6324638 A JP S6324638A JP 16665286 A JP16665286 A JP 16665286A JP 16665286 A JP16665286 A JP 16665286A JP S6324638 A JPS6324638 A JP S6324638A
Authority
JP
Japan
Prior art keywords
film
deposited
contact hole
hole
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP16665286A
Other languages
Japanese (ja)
Other versions
JPH0569294B2 (en
Inventor
Toru Mogami
徹 最上
Hidekazu Okabayashi
岡林 秀和
Eiji Nagasawa
長澤 英二
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
National Institute of Advanced Industrial Science and Technology AIST
Original Assignee
Agency of Industrial Science and Technology
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Agency of Industrial Science and Technology filed Critical Agency of Industrial Science and Technology
Priority to JP16665286A priority Critical patent/JPS6324638A/en
Publication of JPS6324638A publication Critical patent/JPS6324638A/en
Publication of JPH0569294B2 publication Critical patent/JPH0569294B2/ja
Granted legal-status Critical Current

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Abstract

PURPOSE:To completely fill microscopic holes by a method wherein a microscopic hole is partially filled with a conductive film in such a manner that the thickness of the deposited conductive film on the bottom part of the hole is formed uniformly, and the surface of the filled part is almost flattened by forming a conductive film on the non-filled part. CONSTITUTION:After an Si oxide film 2 has been deposited on the Si substrate 1 having the flat surface using a CVU method, a contact hole 3 is formed by performing the commonly used photoresist process and a dry etching process. Then, an Al film 4 is deposited on the whole surface of the substrate 1 by performing an arc discharge type ion-plating method. Under the above-mentioned condition, the Al film 4 is deposited on the whole surface of the substrate 1, a film of uniform thickness is deposited on the stepped part of the contact hole 3 in such a manner that an inclined surface of the prescribed range of angle is formed on the shoulder part of said stepped part. Then, an Al film 4 is deposited by performing a bias sputtering method. As a result, the thickness of the Al film deposited on the bottom part of the contact hole 3 is formed thicker than the film 2, and the Al film on the film 2 is almost flattened.

Description

【発明の詳細な説明】 (産業上の利用分野) 本発明は、コンタクトホールなどの微細ホールを導体膜
で埋め込む方法に関する。
DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method of filling minute holes such as contact holes with a conductive film.

(従来の技術) 半導体装置において配線を行う場合には、表面を保護す
る絶縁膜にコンタクトホールを開けて、その上に導体膜
を堆積するころとによりなされる。最近のLSI等にお
けるコンタクトホールの形成は、露光技術やドライエツ
チング技術の進歩により、膜厚的1μmの絶縁膜に約1
μm角程度のものが可能となっている。このような微細
なコンタクトホール上への導体膜堆積において重要なこ
とは、1つは微細なコンタクトホール内に導体膜を密に
埋めること、もう1つは微細なコンタクトホールに導体
膜が堆積された後、表面が平坦になることである。
(Prior Art) When wiring is provided in a semiconductor device, contact holes are formed in an insulating film that protects the surface, and a conductive film is deposited thereon. Recent advances in exposure technology and dry etching technology have enabled the formation of contact holes in LSIs, etc., to approximately 1 μm in thickness in an insulating film.
It is now possible to have a size on the order of μm square. When depositing a conductor film onto such a fine contact hole, two important things are: one is to densely fill the fine contact hole with the conductor film, and the other is to ensure that the conductor film is not deposited in the fine contact hole. After that, the surface should be flat.

(発明が解決しようとしている問題点)しかし、LSI
でのコンタクトホールは側面が急峻で段差が大きいため
、従来の平行平板型のスパッタ法あるいは蒸着法で導体
膜を堆積させると第2図に示すように、コンタクトホー
ルの段差の肩部分に多くの導体膜自身のシャードー効果
のため段差被覆性が悪くなり、配線が切れたり薄くなっ
たりし易く、LSIの製造歩留まりや信頼性が著しく低
下していた。こうした欠点を防ぐため、微細なコンタク
トホールの側面をテーパー形状として傾斜を持たせ導体
膜が均一に信頼するような形状が用いられるようになっ
てきているが、微細なコンタクトホールの側面に傾斜を
持たせることはLSIの高集積化を阻害することになり
、好ましい改善法ではない。その為、急峻で高アスペク
ト比の溝あるいはコンタクトホールに対して段差被覆性
の良い状態で導体膜を堆積する方法が提案されており、
そのうちの1つとしてプラネタリ−型の基板ホルダーを
用いるスパッタ法がある。プラネタリ−型のスパッタ法
が平行平板型のスパッタ法に比べて、段差被覆性の良い
事は実験的に検証されている。しかし最近、プラネタリ
−型のスパッタ法による微細で深い溝の段差被覆性につ
いてのシュミレーションと実験との比較がニー・アール
・ノイロイサ−(A、 R,Neureuther)氏
らによりアイトリプルイートランザクションオブエレク
トロンデバイス(IEEETrans、 ED、 27
.1449(1980))に報告されている。その報告
によれば輻211m、アスペクト比(深さ7幅)0.5
の溝に対してプラネタリ−型のスパッタ法で膜を堆積す
ると、シャドー効果のために段差被覆性が極めて悪化す
ることが述べられている。更に最近、化学的蒸着(CV
D)法によって形成されるアルミニウムでは上述のスパ
ッタリング法に比較してコンタクトホール内の側壁への
膜の堆積が改善されることが伊藤(T、Ito)氏らに
よりシンポジウムオンブイエルニスアイテクノロジ予稿
集(1982Symp、 onVLSI Techno
logy(Sept、1〜3.1982,0iso、J
apan)Digest of Technical 
Papers、 p、20.)に記載されている。しか
し、形成されたA1膜は抵抗率が高く、かつバラツキが
大きい欠点のあることが報告されており、集積回路配線
として用いるには問題点が多い。
(The problem that the invention is trying to solve) However, LSI
Since the contact hole has steep sides and a large step, when a conductive film is deposited using the conventional parallel plate sputtering method or vapor deposition method, as shown in Figure 2, a large amount of material is deposited on the shoulder of the step of the contact hole. Due to the shadow effect of the conductor film itself, step coverage deteriorates, wiring is easily cut or thinned, and the manufacturing yield and reliability of LSIs are significantly reduced. In order to prevent these drawbacks, the side surfaces of minute contact holes are tapered and sloped to ensure that the conductor film is uniform. This is not a preferable improvement method because it will hinder the high integration of LSI. Therefore, a method has been proposed in which a conductive film is deposited with good step coverage on steep, high aspect ratio grooves or contact holes.
One of them is a sputtering method using a planetary type substrate holder. It has been experimentally verified that the planetary sputtering method provides better step coverage than the parallel plate sputtering method. However, recently, A, R. Neureuther et al. conducted a comparison between simulation and experiment on the step coverage of fine and deep grooves using planetary sputtering method. (IEEE Trans, ED, 27
.. 1449 (1980)). According to the report, the radius is 211m, and the aspect ratio (depth 7 width) is 0.5.
It has been stated that when a film is deposited on the groove by planetary sputtering, the step coverage is extremely deteriorated due to the shadow effect. More recently, chemical vapor deposition (CV
D) Ito et al. reported in the Proceedings of the Symposium on Brnis Eye Technology that aluminum formed by the method has improved film deposition on the side walls of contact holes compared to the sputtering method described above. (1982 Symp, onVLSI Techno
logy(Sept, 1-3.1982, 0iso, J
apan) Digest of Technical
Papers, p, 20. )It is described in. However, it has been reported that the formed A1 film has the drawbacks of high resistivity and large variations, and there are many problems in using it as an integrated circuit wiring.

さらに最近では、バイアススパッタ法を用いてコンタク
トホール部へ導体膜を堆積することにより、コンタクト
ホール内を導体膜により密に埋めることができ、かつ堆
積導体膜の表面を平坦にできることが知られている。し
かしながら、バイアススパッタ法を用いた場合、コンタ
クトホールの埋め込みにはコンタクトホールのアスペク
ト比(深さl直径)に対して限界があり、コンタクトホ
ールのアスペクト比が1以上の場合には埋め込み後にコ
ンタクトホール内の導体膜中に空隙が残り、埋め込み不
完全となることも知られている。
Furthermore, it has recently been known that by depositing a conductor film in the contact hole using bias sputtering, it is possible to fill the inside of the contact hole more densely with the conductor film and to flatten the surface of the deposited conductor film. There is. However, when using the bias sputtering method, there is a limit to the aspect ratio (depth l diameter) of the contact hole when filling the contact hole, and if the aspect ratio of the contact hole is 1 or more, the contact hole will be It is also known that voids remain in the conductor film within the conductor film, resulting in incomplete filling.

本発明の目的は以上述べたごとき、従来の微細(問題点
を解決する勺−手段) 本発明の方法は、表面に堆積された絶縁膜に微細なホー
ルが形成された基板に対して、イオン化蒸着法を用いて
、前記微細ホール底部での堆積導体膜が均一の膜厚で前
記微細ホール深さの一部を導体膜で埋め込む第1の工程
と、バイアススパッタ法を用いて、前記微細ホールのま
だ埋め込まれていない部分を、導体膜により埋め込む第
2の工程とを含んで構成される。
The purpose of the present invention is to solve the conventional microscopic problem (a means for solving the problem) as described above. A first step of filling a part of the depth of the fine hole with a conductive film using a vapor deposition method so that the conductor film deposited at the bottom of the fine hole has a uniform thickness, and a bias sputtering method to fill the deposited conductor film at the bottom of the fine hole with a conductive film having a uniform thickness. and a second step of burying the unfilled portions with a conductive film.

(作用) 本発明においては、アスペクト比が1以上の微細ホール
において、イオン化蒸着法を用いて予めホール内に導体
膜を堆積すると同時に、ホール部の段差肩部への堆積膜
にイオン化蒸着法特有の傾斜面を形成する。これにより
、ホールの児がけ上のアスペクト比は減少する。アスペ
クト比の減少したホール上に、さらにバイアススパッタ
法を用いて導体膜を堆積することにより、バイアススパ
ッタ法のみでは不完全な埋め込みしか実施できなかった
高アスペクト比の微細ホールを導体膜で完全に埋め込む
ことができ、かつ表面の平坦化も同時に実現できる。
(Function) In the present invention, in a fine hole with an aspect ratio of 1 or more, a conductive film is deposited in advance in the hole using an ionization vapor deposition method, and at the same time, a conductor film is deposited on the shoulder of the step in the hole portion using a specific method specific to the ionization vapor deposition method. form an inclined surface. This reduces the aspect ratio of the hole. By further depositing a conductive film on the hole with a reduced aspect ratio using a bias sputtering method, we can completely fill the fine hole with a high aspect ratio, which could only be incompletely filled with the bias sputtering method. It can be embedded and the surface can be flattened at the same time.

(実施例) 以下、本発明の実施例を図面を参照して説明する。(Example) Embodiments of the present invention will be described below with reference to the drawings.

第1図(a)〜(c)は本発明の一実施例を工程を追っ
て順次示した模式的断面図である。
FIGS. 1(a) to 1(c) are schematic sectional views sequentially showing steps of an embodiment of the present invention.

第1図(a)は平坦な表面を持つシリコン基板1上に厚
さ約111mのシリコン酸化膜2をCVD法で堆積した
後、通常のフォトレジスト工程とドライエツチング工程
により直径1pmのコンタクトホール3を形成した状態
を示す。
In FIG. 1(a), a silicon oxide film 2 with a thickness of about 111 m is deposited on a silicon substrate 1 with a flat surface by the CVD method, and then a contact hole 3 with a diameter of 1 pm is formed by a normal photoresist process and dry etching process. This shows the state in which it has been formed.

次いで第1図(b)に示すようにアーク放電用イオン化
電流2OA、基板バイアス電圧−3kVなる条件下にお
いて、アルミニウムソースを用いてアーク放電型イオン
ブレーティング法によりアルミニウム膜4を基板1表面
全体に、厚さ約0.51J、m堆積する。当該条件下で
堆積するアルミニウム膜は、コンタクトホール底部には
均一な膜厚で堆積し、かつコンタクトホール段差肩部に
は傾斜角40°〜60°の傾斜面を形成するように堆積
する。
Next, as shown in FIG. 1(b), an aluminum film 4 is applied to the entire surface of the substrate 1 by an arc discharge ion blating method using an aluminum source under conditions of an arc discharge ionization current of 2 OA and a substrate bias voltage of -3 kV. , about 0.51 J, m thick is deposited. The aluminum film deposited under these conditions has a uniform thickness at the bottom of the contact hole, and is deposited so as to form an inclined surface with an inclination angle of 40° to 60° at the shoulder of the contact hole step.

次いで第1図(C)に示すように、アルミニウムターゲ
ット電力1.OkW、基板バイアス電圧−600v、ア
ルゴン圧3mTorrなる条件下においてバイアススパ
ッタ法によりアルミニウム膜4をさらに約0.5μm堆
積する。当該条件下では、コンタクトホール底部に堆積
するアルミニウム膜の膜厚はシリコン酸化膜2の上に堆
積するアルミニウム膜の膜厚の2倍となり、コンタクト
ホールを有するシリコン酸化膜上のアルミニウム膜はほ
ぼ平坦になる。
Next, as shown in FIG. 1(C), the aluminum target power 1. An aluminum film 4 of about 0.5 μm is further deposited by bias sputtering under conditions of OKW, substrate bias voltage of −600 V, and argon pressure of 3 mTorr. Under these conditions, the thickness of the aluminum film deposited at the bottom of the contact hole is twice the thickness of the aluminum film deposited on the silicon oxide film 2, and the aluminum film on the silicon oxide film with the contact hole is almost flat. become.

前記実施例においては、アルミニウム膜な被着したが何
もこれに限る必要はなく、モリブデン等の他の金属、不
純物をドープした多結晶シリコンやシリサイド等の合金
も用いることができる。
In the embodiment described above, an aluminum film is deposited, but there is no need to be limited to this; other metals such as molybdenum, and alloys such as polycrystalline silicon doped with impurities and silicide can also be used.

また前記実施例では基板とそのすぐ上の配線(第−層配
線)を接続するコンタクト電極を形成したが、これに限
らず第−層とその上の第二層配線あるいは更にその上の
配線とを接続する微細なスールーホールに導体膜を良好
にうめこむ場合などに適用できる。
Furthermore, in the above embodiment, a contact electrode was formed to connect the substrate and the wiring immediately above it (layer wiring). This method can be applied to cases where a conductive film is well embedded in a fine through-hole that connects.

(発明の効果) 以上説明したように、本発明はアスペクト比が1以上の
微細なホールに導体膜をうめこむ場合に、アーク放電型
イオンブレーティング法とバイアススパッタ法とを組み
合わせて用いることにより、バイアススパッタ法のみで
は不可能であったアスペクト比1以上の微細なホールの
埋め込みを実現できる。
(Effects of the Invention) As explained above, the present invention uses a combination of arc discharge type ion blating method and bias sputtering method when embedding a conductive film into a fine hole with an aspect ratio of 1 or more. It is possible to fill minute holes with an aspect ratio of 1 or more, which was impossible with bias sputtering alone.

【図面の簡単な説明】[Brief explanation of drawings]

第1図(a)〜(c)は本発明の一実施例を工程を追っ
て順次示した模式的断面図、第2図は、従来のスパッタ
法あるいは蒸着法により導体膜を急峻な側面を有するコ
ンタクトホールの形成された基板上に堆積した場合のコ
ンタクトホール部の模式的断面国費ある。 図中の番号は以下のものを示す。 1・・・シリコン基板 2・・・シリコン酸化月莫 3・・・コンタクトホール 4・・・アルミニウム膜 第  1  図
FIGS. 1(a) to (c) are schematic cross-sectional views sequentially showing one embodiment of the present invention step by step, and FIG. 2 shows a conductor film having a steep side surface formed by a conventional sputtering method or vapor deposition method. There is a schematic cross-section of a contact hole portion when deposited on a substrate with a contact hole formed therein. The numbers in the figure indicate the following. 1...Silicon substrate 2...Silicon oxide layer 3...Contact hole 4...Aluminum film Fig. 1

Claims (1)

【特許請求の範囲】[Claims] 表面に堆積された絶縁膜に微細ホールが形成された基板
に対して、イオン化蒸着法を用いて、前記微細ホール底
部での堆積導体膜が均一の膜厚で前記微細ホール深さの
一部を導体膜で埋め込む第1の工程と、バイアススパッ
タ法を用いて、前記微細ホールのまだ埋め込まれていな
い部分を導体膜により埋め込む第2の工程とを含むこと
を特徴とする微細ホールうめこみ方法。
Using an ionization vapor deposition method for a substrate in which fine holes are formed in an insulating film deposited on the surface, a conductor film deposited at the bottom of the fine hole is formed with a uniform thickness to cover part of the depth of the fine hole. A method for filling a fine hole, the method comprising: a first step of filling with a conductive film; and a second step of filling an unfilled portion of the fine hole with a conductive film using a bias sputtering method.
JP16665286A 1986-07-17 1986-07-17 Microscopic hole filling method Granted JPS6324638A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16665286A JPS6324638A (en) 1986-07-17 1986-07-17 Microscopic hole filling method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16665286A JPS6324638A (en) 1986-07-17 1986-07-17 Microscopic hole filling method

Publications (2)

Publication Number Publication Date
JPS6324638A true JPS6324638A (en) 1988-02-02
JPH0569294B2 JPH0569294B2 (en) 1993-09-30

Family

ID=15835234

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16665286A Granted JPS6324638A (en) 1986-07-17 1986-07-17 Microscopic hole filling method

Country Status (1)

Country Link
JP (1) JPS6324638A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60233840A (en) * 1984-05-04 1985-11-20 Nec Corp Coating method for stepwise difference

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60233840A (en) * 1984-05-04 1985-11-20 Nec Corp Coating method for stepwise difference

Also Published As

Publication number Publication date
JPH0569294B2 (en) 1993-09-30

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