JPS632467A - Synchronizing signal generation circuit - Google Patents

Abstract

PURPOSE:To reduce the capacity of a ROM without changing the size of a circuit by determining the positions of a horizontal synchronizing signal, a vertical synchronizing signal and a burst signal on the basis of a sampling clock whose phase is locked and simplifying the control of ROM addresses. CONSTITUTION:A horizontal synchronizing signal (HD) and a vertical synchronizing signal (VD) generated from a receiver and a resampling clock phase-locked with the HD arrive at respective input terminals 1-3. A horizontal synchronizing signal counter 10 determines the position of the signal HD. A burst position adjusting counter 12 determines the position of a burst signal from the output of the counter 10. A burst address counter 14 determines the address of a burst signal from the output of the counter 12. A vertical synchronizing signal period deciding circuit 11 decides the period of the signal VD and a vertical synchronizing signal Counter 13 determines the position of the signal VD from the output of the circuit 11. An AND circuit 15 determines the addresses of the signals HD, VD from the outputs of the counters 10, 13. A ROM 6 inputs these addresses and outputs digital data. A black burst signal is obtained from the output.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a synchronization signal generation circuit that uses a digital memory to generate a synchronization signal in an apparatus that digitally processes television signals.

[Conventional technology]

FIG. 4 shows, for example, the horizontal synchronizing signal (HD) shown in FIG.
Burst signal and vertical synchronization signal (VD) shown in Figure 3
This figure shows a general circuit that digitally generates a high-definition television black burst signal consisting of a resample clock that is phase-locked to HD and VDSHD in a receiver.

In FIG. 4, 1 is an HD input terminal, 2 is a VD input terminal, 3 is a resample clock input terminal, 4 is a terminal 1, 2 .
A reset circuit that generates a reset pulse for the address counter 5 from the signal 3, a ROM that uses the output of the address counter 5 as an address input, 7 a D/A converter that uses the output of the ROM 6 manually, and 8 a D/A A low-pass filter receives the output of the converter 7, and 9 is an output terminal of the low-pass filter 8, which is a black burst signal output terminal.

Next, the operation will be explained. HD generated in the receiver,
Resample clocks phase-locked to VD and HD arrive at each input terminal 1, 2.3. The reset circuit 4 generates a reset pulse for resetting the address counter 5 once per frame at the beginning of the first line from the input signal arriving at the input terminals 1, 2, and 3. The address counter 5 up-counts the resample clock until it is reset by the output signal of the reset circuit 4. In the ROM 6, digital values of the waveform of the black burst signal shown in FIGS. 2 and 3 are written for one frame. The ROM 6 outputs digital data to the D/A converter 7 according to the address specified by the address counter 5.

The D/A converter 7 converts the output signal of the ROM 6 into an analog quantity. The output signal of the D/A converter 7 is smoothed by a low pass filter 8. In this way, the black burst signal shown in FIGS. 2 and 3 can be obtained at the black burst signal output terminal 9.

[Problem that the invention seeks to solve]

Since the conventional synchronization signal generation circuit is configured as described above, it is necessary to count the resample clock for one frame period, which has the problem of requiring the use of a large-capacity, high-speed R0M. - This invention was made to solve the above problems, and it is possible to achieve a small capacity high-speed RO with the same circuit scale as the conventional one.
The object of the present invention is to obtain a synchronization signal generation circuit that can be configured using M.

Means for Solving Problem C] The synchronization signal generation circuit according to the present invention can be used for HD, VD, HD
The input signal is a resample clock phase-locked to
A horizontal synchronization signal generation counter that determines the position of the horizontal synchronization signal, a burst position adjustment counter that determines the position of the burst signal from the output of the horizontal synchronization signal generation counter, and an address of the burst signal from the output of the burst position adjustment counter. a burst address counter that determines the vertical synchronization signal period; a vertical synchronization signal period determination circuit that determines the vertical synchronization signal period; a vertical synchronization signal generation counter that determines the position of the vertical synchronization signal from the output of the vertical synchronization signal period determination circuit; A logic circuit that determines the address of the horizontal synchronization signal and vertical synchronization signal from the output of the signal generation counter and the output of the pJ1 signal generation counter, and address control using the output of the burst address counter and the output of the 8-bit logic circuit. RO to be
ROM, a D/A converter that converts the digital output of the ROM into an analog quantity, and a low-pass filter that smoothes the output of the D/A converter.

[Effect]

In the synchronization signal generation circuit according to the present invention, HD.

From the resample clock phase-locked with VD and HD,
Since the positions of the horizontal synchronization signal, vertical synchronization signal, and burst signal are determined, ROM address control can be easily performed.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings. 1st
In the figure, 1 is the HD input terminal, 2 is the VD input terminal, and 3 is the HD input terminal.
is the resample clock input terminal. 10 is a horizontal synchronization signal generation counter which receives the signal of HD input terminal 1 and the signal of resample clock input terminal 3; 12 is terminal 3;
14 is a burst count 11 counter whose inputs are the signal of terminal 3 and the output of counter 10;
a burst address counter whose input is the output of
13 is a vertical synchronization signal period determination circuit which receives the signal from HD input terminal 1 and the signal from VD input terminal 2 as input, and 13 represents a vertical synchronization signal generation circuit which receives the signal from terminal 3 and the output of vertical synchronization signal determination circuit 11 15 is an AND circuit whose inputs are the output of counter 10 and the output of counter 13, 6 is a ROM whose address inputs are the output of counter 14 and the output of AND circuit 15, and 7 is the signal of terminal 3 and ROM 6. 8 is a low-pass filter that receives the output of the D/A converter 7, and 9 is an output terminal of the low-pass filter 8, which is a black burst signal output terminal.

Next, the operation will be explained. HD generated in the receiver,
Resample clocks phase-locked to VD and HD arrive at each input terminal 1, 2.3. The horizontal synchronization signal generation counter 10 is initialized at the starting edge of the horizontal synchronization signal HD of the input signal of the input terminal 1 (section A in FIG. 2), and starts counting the resample clock of the input signal of the input terminal 3. Then, the horizontal synchronizing signal period shown in FIG. 2 continues to be counted, and the counting is stopped at the time corresponding to part B in FIG. 2. The A adjustment counter 12 is
It is initialized by the end edge of the output of the counter 10 at the counting stop position of the counter 10, and starts counting the resample clock, and when a predetermined time elapses, that is, the time corresponding to the 0 part in FIG. The burst address counter 14, which performs the stopping operation, is the counter 12.
At the count stop position, initialized by the end edge of the output of counter 12, the resample clock starts counting and continues counting the burst signal period shown in FIG. 2, corresponding to section D in FIG. Performs an action to stop counting at the time.

On the other hand, the vertical synchronization signal determination circuit 11 determines the first field and the second field from the HD and VD input to the input terminal 1.2. And 1125 lines and 1 to 3
HD for 4 lines up to line and 563 line-5
Detects 4 lines of HD up to 66 lines. The vertical synchronization signal generation counter 13 includes two types of counters, one for the first field and one for the second field (not shown).

The counter for the first field is initialized at the starting edge of the HD of 4 lines from the 1125th line to the 3rd line and starts counting the resample clock, and its output is the time corresponding to part E in Figure 3. It falls at the time corresponding to the F section, and rises at the time corresponding to the F section.

Then, the counter for the first field stops counting at the time corresponding to the F section. The counter for the second field consists of two types of counters (referred to as counter ■ and counter ■).
It is initialized by the page and starts counting the resample clock. The output of the counter 2 falls at a time corresponding to the 0 section in FIG. 3, and rises at a time corresponding to the H section in FIG. Then, the counter I stops counting at a time corresponding to the H section. The output of the counter 2 falls at a time corresponding to the 1st part in FIG. 3, and rises at a time corresponding to the 5th part in FIG. Then, the counter {circle around (2)} stops counting at the time corresponding to the fifth copy. The output signal of the counter 13 is the logical product of the output of the counter for the first field and the output of the two counters for the second field. The AND circuit 15 takes the logical product of the output signal of the counter 10 and the output signal of the counter 13.
(c) shows the output signal of the counter 10, the output signal of the counter 13, and the output signal of the AND circuit 15.

The frequency of the resample clock is fe = 960 f (
rH is the horizontal frequency), the burst signal has a frequency f a =384 f M and a frequency of 8 as shown in Figure 2.
There is a cycle. Therefore, the burst signal period is 8/fIl, and the total number of samples in the parse Hε period in which the burst signal is sampled using the resampling clock is (8/fIl).
a) x f, =20 (pieces).

Furthermore, since fc/f m =2.5, the number of samples per cycle of the burst signal is 2.5.

Therefore, there are five sampling points in two cycles of the burst signal, and as shown in FIG. 6, the phases of the sampling points return to the same phase in two cycles of the burst signal. Therefore, sampling data of 5 flt[ is generated in two cycles of the burst signal.

Since the total number of samples is 20, five types of sampling data are repeated four times.

In this case, since five types of outputs from the burst address counter 14 corresponding to the pulse Hi number in FIG. 2 are sufficient, three bits are sufficient. Furthermore, since the output signal of the AND circuit 15 is a binary signal as shown in FIG. 5(C), one bit is sufficient. Then, the output of the AND circuit 15 and the counter 1
Since the outputs of 4 are independent, all the signals shown in FIGS. 2 and 3 can be expressed by 4-bit addresses.

The ROM 6 uses the output of the AND circuit 15 and the output of the counter 14 as address inputs, and outputs digital data corresponding to the amplitudes of the signals shown in FIGS. 2 and 3. D/A converter 7
converts the output data of the ROM 6 into an analog quantity. Low-pass filter 8 smoothes the output of D/A converter 7. In this way, the blank burst signal shown in FIGS. 2 and 3 is obtained at the black burst signal output terminal 9 of the output of the low-pass filter 8.

〔Effect of the invention〕

As described above, according to the present invention, in a synchronization signal generation circuit that generates a black burst signal for a high-definition television, by determining the temporal positions of a horizontal open M signal, a vertical synchronization signal, and a burst signal, Since address control is made easy, the circuit can be constructed using a small capacity high speed ROM. Further, the circuit scale is the same as the conventional one, and the circuit configuration is easy.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a synchronization signal generation circuit according to an embodiment of the present invention, FIG. 2 is a diagram showing a horizontal synchronization signal and burst signal of a high-definition television, and FIG. 3 is a diagram showing a vertical synchronization signal of a high-definition television. 4 is a circuit diagram of a conventional synchronization signal generation circuit,
Figure 5 (a), (bl, (C1 is a diagram showing the output of the horizontal synchronization signal generation counter, the output of the vertical synchronization signal generation counter, and the output of the AND circuit, respectively. Figure 6 is sampling using the burst signal and resample clock. In the figure, 1 is an HD input terminal, 2 is a VD input terminal, 3 is a resample clock input terminal, 4 is a reset circuit, 5 is an address counter, 6 is a ROM, and 7 is a D/A converter, 8 is a low-pass filter, 9 is a black burst signal output terminal, 1
0 is a horizontal synchronizing signal generation counter, 11 is a vertical synchronizing signal period determination circuit, 12 is a burst position adjustment counter, 13 is a vertical synchronizing signal generation counter, 14 is a burst address counter, and 15 is an AND circuit. Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (1)

[Claims] (1) In a synchronization signal generation circuit that generates a high-definition television black burst signal through digital processing from a horizontal synchronization signal, a vertical synchronization signal, and a resample clock that is phase-synchronized with the horizontal synchronization signal, A horizontal synchronization signal generation counter that determines the position of the horizontal synchronization signal; a burst position adjustment counter that determines the position of the burst signal from the output of the horizontal synchronization signal generation counter; and a burst position adjustment counter that determines the address of the burst signal from the output of the burst position adjustment counter. A burst address counter that determines the vertical synchronization signal period, a vertical synchronization signal period determination circuit that determines the vertical synchronization signal period from the input horizontal synchronization signal and vertical synchronization signal, and a vertical synchronization signal period determination circuit that determines the position of the vertical synchronization signal from the output of the vertical synchronization signal period determination circuit. a logic circuit that determines the addresses of the horizontal synchronization signal and the vertical synchronization signal from the output of the horizontal synchronization signal generation counter and the output of the vertical synchronization signal generation counter; and the output of the burst address counter; A ROM whose address is controlled by the output of the logic circuit, and a D/D converter that converts the digital output of the ROM into an analog quantity.
A synchronization signal generation circuit comprising: an A converter; and a low-pass filter that smoothes the output of the D/A converter.