JPS63252013A - Constant current switching circuit - Google Patents

Abstract

PURPOSE:To switch a large output current at a high speed with low current consumption by providing a speed compensating circuit which is controlled with an input signal and grounds the base of a reference transistor(TR) when the TR is turned off. CONSTITUTION:When an 'L' input signal VIN is supplied to an input circuit 15 and the speed compensating circuit 19 through an input terminal 11, the output sides of the circuits 15 and 19 turn off. Consequently, the potential at a node N11 is raised with a constant current I0 outputted from a constant current source circuit 14 and the reference TR 17 and output TRs 18-1-18-N turn on, so that output currents I11-I1N flow to output terminals 13-1-13-N. If the input signal VIN raises abruptly to 'H' in this state, the circuit 15 turns on and the constant current I0 flows to the ground side. At this time, a capacitor CS is discharged through the circuit 19 so that a current ip flows to the ground side. Consequently, the reference TR 17 and output TRs 18-1-18-N constituting a current mirror circuit turn off instantaneously.

Description

Detailed Description of the Invention (Industrial Field of Application) The present invention applies a constant output current to a load such as a light emitting diode array (hereinafter referred to as an LED array).

This relates to a constant current switching circuit that provides off-supply.

(Conventional Technology) Conventionally, as a technology in this field, Analysis and Design on Analog Ingrated Circuits (Analysis and DeSil
;in Of Analog Integrated
C1tCuitS) 2nd edition (1977), John Wiey & Song (John Wiey & 5)
ons) (USA) Paul Earl Gray and Ropert G. Mayer (Pau IR, Gray a
nd Robert G, Meyer) P, 197-
There was something described in 267. The configuration will be explained below using figures.

FIG. 2 is a circuit showing an example of the configuration of a conventional current mirror type constant current switching circuit.

This constant current switching circuit has an input terminal 1 to which an input signal VIN is input, a power supply terminal 2 to which a power supply voltage vCC is applied, and output terminals 3-1 to 3-N to output a plurality of output currents 11 to IN. A node N1 is connected to the power supply terminal 2 via a constant current source circuit 4 that outputs a reference current IO, and an input circuit 5 is connected between the node N1 and the input terminal 1. Drive N to node N1
The base of a PN type transistor 6 is connected. The input circuit 5 is a circuit that controls the sinking of current on the node N1 side based on the input signal VIN.

A current mirror circuit is connected to the node N1 and the emitter side of the transistor 6. This current mirror circuit consists of NPN transistors that serve as a reference.
It has PN type output transistors 8 to 8-N and a plurality of resistors RO and R1 to RN. The reference transistor 7 has its collector connected to the node N1, its emitter connected to the ground via the resistor RO, and its base connected to the emitter of the transistor 6 via the node N2, and further connected to each output transistor 8-1 to the node N2. The bases of ~8-H are commonly connected. Each output transistor 8-
1 to 8-N, their collectors are connected to each output terminal 3-1 to
3-H, and their respective emitters are connected to ground via respective resistors R1 to RN. Loads RJI 1 to R, ll N to which a power supply voltage vCC is applied are connected to each output terminal 3-1 to 3-H.

FIG. 3 is an output current response waveform diagram of FIG. 2, and the operation of FIG. 2 will be explained with reference to this diagram.

The constant current switching circuit shown in FIG. 2 switches the supply path of the constant current IO from the constant current source circuit 4 to the input circuit 5 side or the current mirror circuit side according to the state of the input signal VIN applied to the input terminal 1. It performs a switch. That is, when the input signal VIN is at a low level (hereinafter referred to as "L"), the output impedance of the input circuit 5 increases, so the potential of the node N1 increases due to the constant current IO, and the transistor 6 turns on. , the potential of node N2 rises. Then, the reference transistor 7 and the output transistors 8-1 to 8-N are turned on, and a constant current ■
Output current 11~IN proportional to 0 is applied to each output terminal 3-1~
Flows to 3-H. The values of the output currents 11 to IN are expressed as follows, assuming that the transistors 7.8-1 to 8-N are completely the same including the emitter area.

When VIN = "L'"...(1) However, the subscript n of each code is 1.2. ..., NvT; Threshold value of transistors 7, 8-1 to 8-H Also, when the input signal VTN is at a high level (hereinafter referred to as "H"), the input circuit 5 sucks a constant current ■0. , the potential of node N1 decreases, turning transistor 6 off, thereby turning reference transistor 7 and output transistors 8-1 to 8-N off, and output currents 11 to IN become zero.

(Problems to be Solved by the Invention) However, the circuit with the above configuration has the following problems.

In order to increase the output current 11 to IN, the emitter area of the output transistors 8-1 to 8-H should be increased relative to the reference transistor 7, or a large number of output transistors 8-1 to &-N should be It is necessary to connect them in parallel as shown in the figure, but as a result, the capacitance C generated at node N2 due to the junction capacitance and stray capacitance of transistors 8-1 to 8-H, etc.
8 becomes large, which causes a problem that the response characteristics of the output current In (=N1 to IN) deteriorate. That is, as shown in FIG. 3, when a pulse-like input signal VIN is applied to the input terminal 1, the output current response waveform becomes fast because the transistor 6 acts as a buffer with respect to the rise of the input signal VIN. , since the capacitance C8 at the node N2 is large for the falling edge, the waveform decays exponentially with a large time constant due to the accumulated charge. If the fall time of the output current In becomes longer in this way, high-speed switching becomes impossible.

Therefore, in order to improve this problem, a proposal has been made to connect resistor R8 to node N2 to form a discharge path for the accumulated charge, but this does not result in a technically satisfactory result, as the current consumption of the circuit increases. There wasn't.

The present invention solves the problems that the prior art had, such as deterioration of the pulse response waveform of the output current, decrease in switching speed,
The present invention also provides a constant current switching circuit that solves the problem of increased current consumption.

(Means for Solving the Problems) In order to solve the above problems, the present invention provides a reference transistor whose collector is supplied with a constant current, and a reference transistor that controls the constant current based on an input signal to turn on the reference transistor. , a current mirror type constant current comprising an input circuit for turning off, and an output transistor whose base is commonly connected to the base of the reference transistor and outputs an output current proportional to the constant current controlled on and off from the collector. The switching circuit is provided with a speed compensation circuit which is controlled by the input signal and whose base is grounded when the reference transistor is off.

(Function) According to the present invention, since the constant current switching circuit is configured as described above, the speed compensation circuit grounds the base of the reference transistor when it is off, and transfers the accumulated charge of the capacitance parasitic to the base to the ground side. Works like a discharge. This shortens the fall time of the output current, allowing high-speed switching of a large output current with low current consumption. Therefore, the above-mentioned problem can be eliminated.

(Embodiment) FIG. 1 is a circuit diagram of a current mirror type constant current switching circuit showing an embodiment of the present invention.

This constant current switching circuit includes an input terminal 11 to which an input signal VIN is input, a power supply terminal 12 to which a power supply voltage vCC is applied, and a plurality of output currents 111 to II as in the conventional case.
It has output terminals 13-1 to 13-N that output N, and a node Nil is connected to its power supply terminal 12 via a constant current source circuit 14 that outputs a reference constant current IO. An input circuit 15 is connected between input terminals 11, and its nodes N11. The base of the driving NPN transistor 16 is connected to the base of the driving NPN transistor 16. The collector of the transistor 16 is connected to the power supply terminal 12, and the emitter thereof is connected to the node N12. The input circuit 15 is a circuit that controls the sinking of current on the node N11 side based on the input signal VIN.

A current mirror circuit is connected to the nodes Nil and N12. This current mirror circuit includes an NPN reference transistor 17, N NPN output transistors 18 to 18-N, and a plurality of resistors RO, R1 to
Has an RN. The reference transistor 17 has its collector connected to the node Nll, its emitter connected to the ground via the resistor RO, and its base connected to the node N12, and further connected to the node N12 by each output transistor 18-.
The bases of 1 to 18-N are commonly connected.

Each of the output transistors 18-1 to 18-N has its collector connected to each output terminal 13-1 to 13-N, and its emitter connected to ground via each resistor R1 to RN. There is. Each output terminal 13-1 to 13-N
is a load RJI)11 to which a power supply voltage vCC is applied.
RJI IN is connected.

An input side of a speed compensation circuit 19 is connected to the input terminal 11, and an output side of the circuit 19 is connected to a node N12. This speed compensation circuit 19 is based on the input signal VIN,
This circuit controls the sinking of current ip on node N12.

A capacitance C8 such as a junction capacitance or a stray capacitance is parasitic to the node N12.

FIG. 4 is a circuit diagram showing an example of the configuration of the input circuit 15 shown in FIG. 1. This input circuit 15 is constructed of a totem pole type gate and has an input terminal 20 connected to the input terminal 11 in FIG. 1, and an output terminal 21 connected to the node Nll.
, and a power supply terminal 22 to which a power supply voltage vCC is applied, and an NP between the input/output terminal 20.21 and the power supply terminal 22.
N-type transistors 23, 24, 25, 26, resistors 27.
28, 29, 30, and diodes 31, 32 are connected. That is, a resistor 27°28,
30 are connected in parallel, and the transistor 23 is connected to the resistor 27.
The emitter of the transistor 23 is connected to the input terminal 20, and the collector thereof is connected to the base of the transistor 24. The transistor 24 has its collector connected to the resistor 28 and the base of the transistor 25, and its emitter connected to the base of the transistor 26 and to ground via the resistor 29. A resistor 30 is connected between the output terminal 22 and the ground.
The collector and emitter of the transistor 25, the forward diode 31, and the collector and emitter of the transistor 26 are connected in series, and the collector of the transistor 26 is connected to the output terminal 21 via the reverse diode 32.

FIG. 5 is a circuit diagram showing an example of the configuration of the speed compensation circuit 19 shown in FIG. 1. This speed compensation circuit 19 is composed of an oven collector type and a gate, and its input/output terminals 30.3
1 and the power supply terminal 32, an NPN transistor 33.3
4.35 and resistors 36, 37, and 38 are connected.

That is, the transistor 33 has its emitter connected to the input terminal 30, its base connected to the power supply terminal 32 via the resistor 36, and its collector connected to the base of the transistor 34. The transistor 34 has its collector connected to the power supply terminal 32 through a resistor 37, and its emitter connected to the base of a transistor 35 and to ground through a resistor 38. The transistor 35 has its collector connected to the output terminal 31 and its emitter connected to the ground.

FIG. 6 is an output current response waveform diagram of FIG. 1, and the operations of FIGS. 1, 4, and 5 will be explained with reference to this diagram.

"When the input signal VIN of Ll+ is supplied to the input circuit 15 and the speed compensation circuit 19 through the input terminal 11 in FIG. 1, the transistor 23 in the input circuit 15 in FIG. becomes "L" and transistor 24 turns off. When transistor 24 turns off, its collector becomes "H" and its emitter becomes "L", turning transistor 25 on and transistor 26 off. Then, the collector of the transistor 26 becomes "H" and the diode 32 turns off.Furthermore, the input signal VIN
When is "L", in the speed compensation circuit 19 of FIG. 5, the transistor 33 is turned off and its collector becomes "IIL".
Therefore, the transistor 34 is turned off. When the transistor 34 is turned off, its emitter becomes "L" and the transistor 35 is turned off.

When the output sides of the input circuit 15 and the speed compensation circuit 19 are turned off, the potential of the node N11 rises due to the constant current 0 output from the constant current source circuit 14 in FIG. 1, and the transistor 16 is turned on. The potential of node N12 rises. When the potential of the node N12 rises, the reference transistor 11 and the output transistors 18-1 to 18-N are turned off, and each output current 11 is proportional to the constant current IO.
1 to IIN flow to output terminals 13-1 to 13-N, respectively. The value of this output current 111 to IIN (=11n) is (resistance ratio (RO/Rn) or reference transistor 1
The emitter area ratio of the output transistors 18-1 to 18-H to 7)×(constant current IO).

Here, the subscript n of 11n and Rn is 1, 2, .・、
It represents the value of H.

When the input signal VIN suddenly rises to "H" from this state, the transistor 23 of the input circuit 15 in FIG. 4 is turned off, the transistor 24 is turned on, the transistor 25 is turned off, and the transistor 26 is turned on. To become
The diode 32 is turned on, and this diode 32
The constant current IO shown in FIG. 1 is sucked into the ground through the capacitor.

Here, if the potential of the output terminal 21 when the diode 32 is in the on state is set to be equal to or lower than the base-emitter voltage of the transistor 16, the potential drop at the node N11 turns the transistor 1G off, and the voltage at the node N12 becomes lower. The potential decreases and the reference transistor 17 and output transistors 18-1 to 18-N turn off,
Each output current 111 to IIN decreases to zero. At this time, in the speed compensation circuit 19 of FIG.
is in the off state, and the transistor 34 is in the on state, causing the transistor 35 to be in the on state. Therefore, the accumulated charge in the capacitor C8, which is a factor in degrading the response characteristics, is discharged to the ground side through the transistor 35 in the form of current ip. Therefore, the reference transistor 17 and the output transistors 18-1 to 18-N that constitute the current mirror circuit instantaneously change from the on state to the off state. The falling time of the output current waveform of this embodiment shown in is shortened, and as a result, a large output current 11
High-speed switching of 1 to IIN (=11n) is possible.

Further, in this embodiment, when the input signal VIN is "H", the input circuit 15 sucks the constant current 0, and the transistor 16
In order to turn off the speed compensation circuit 19, there is a capacity tcs.
The accumulated charge of is simply absorbed in the form of current ip.

This current ip does not flow when the input signal VIN is "Lll". Furthermore, the input circuit 15 and the speed compensation circuit 19 are composed of several transistors, resistors, etc. Therefore, the effect of low current consumption can be expected.

Note that the present invention is not limited to the illustrated embodiment, and various modifications are possible. Examples of such modifications include the following.

(i) FIG. 7 is a circuit diagram in which the input circuit 15 and speed compensation circuit 19 of FIG. 1 are integrated. In this circuit, the fourth
Using the input circuit 15 shown in the figure, by commonly connecting the bases of the transistors 35 in the speed compensation circuit 19 shown in FIG. It has the same functions as those shown in FIGS. 7th like this
With the circuit configuration shown in the figure, the circuit configuration can be simplified and the current consumption can be reduced accordingly.

(ii) Output transistors 18-1 to 18-N are set to 1
It is also possible to modify the constant current circuit shown in FIG. 1 to other configurations, such as having only one circuit, or to configure the input circuit 15 and speed compensation circuit 19 to have circuit configurations other than those shown.

(Effects of the Invention) As explained in detail above, according to the present invention, the conventional current mirror type constant current switch which switches the constant current supply path and turns on and off the output ionizing current proportional to the constant current value. A speed compensation circuit is provided in the switching circuit, so even when increasing the emitter area of the output transistor to obtain a large output current, or when connecting multiple output transistors in parallel, the current consumption does not increase. High-speed current switching operation becomes possible. Therefore, it can be applied to various circuits such as integrated circuits.

[Brief explanation of drawings]

Figure 1 is a circuit diagram of a constant current switching circuit showing an embodiment of the present invention, Figure 2 is a circuit diagram of a conventional constant current switching circuit, Figure 3 is an output current response waveform diagram of Figure 2, and Figure 4. is a circuit diagram of the input circuit in Figure 1, Figure 5 is a circuit diagram of the speed compensation circuit in Figure 1, Figure 6 is an output current response waveform diagram in Figure 1,
FIG. 7 is a circuit diagram of another input circuit and speed compensation circuit shown in FIG. 14... Constant current source circuit, 15... Input circuit, 16... Transistor, 17...
・Reference transistor, 18-1 to 18-N...
Output transistor, 19...speed compensation circuit, I
O... Constant current, ■11~IIN (=11n
')...Output current, VIN...Input signal. Applicant's agent Yasushi Kakimoto Figure 1 Input path Figure 4 The difference in Figure 1 The output circuit Figure 5 Figure 1 Output lightning; Figure 7: Pond input circuit and U disdain compensation circuit

Claims (1)

[Scope of Claims] A reference transistor whose collector is supplied with a constant current; an input circuit that controls the constant current based on an input signal to turn on and off the reference transistor; and a base connected to the base of the reference transistor. A constant current switching circuit comprising an output transistor that is commonly connected and outputs an output current that is controlled to turn on and off from a collector, and a speed compensation circuit that is controlled by the input signal and grounds the base of the reference transistor when it is turned off. A constant current switching circuit characterized by: