JPS63252480A - Vertical mos field-effect transistor - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Industrial Application Field] This invention relates to a vertical MOS field effect transistor (vertical MOSFET).
SFET).

[Conventional technology]

FIG. 2 shows a conventional vertical MO5FET. In the figure,
1 is an n-type (first conductivity type) substrate, 2 is an n drain region formed on one main surface of the substrate 1, and 3 is a p region formed in a 7-trix shape on the other main surface of the substrate. (Second conductivity type) channel region, 4 is an n source @ region formed in this P channel region, 5 is an oxide film formed to cover the main surface between adjacent p channels and a part of the n source region , 6 is a gate electrode formed on this oxide film, 7 is an insulating film formed to cover this gate electrode, and 8 is a source electrode attached to the n source region 5.

Since the conventional vertical MOS field effect transistor is constructed as described above, when a positive potential higher than the threshold of the vertical MOS field effect transistor is applied to the gate electrode 6, the surface portion of the P channel region 3 is inverted to an n channel. , the current is shown in Figure 2 (h).

As shown by the broken line in (C), the flow first flows vertically from the n+ drain region 2 toward the gate electrode 6, then changes direction in the region between adjacent p channel regions 3, and the n
It passes through the channel and reaches the n source region 5.

In FIG. 2(b), a chain line indicates a depletion layer that occurs when the potential applied to the gate electrode does not reach the threshold value, that is, in the OFF state.

[Problem that the invention seeks to solve]

A conventional vertical MOS field effect transistor is shown in Fig. 2(a).
Since a plurality of P channel regions 3 are formed in a matrix as shown in FIG. ) is the ratio of the distance between adjacent p-channel regions 3 shown in the 82-82 line cross-sectional view. The spread of the depletion layer in the region is not constant. As a result, as shown by the dashed line in Fig. 2(C),
There is a problem in that the electric field is concentrated at a position equidistant from each P channel region 3, and the avalanche breakdown voltage is low at the location where the electric field is concentrated.

The present invention was made to solve the above-mentioned problems, and an object of the present invention is to obtain a vertical MOS field effect transistor with high breakdown voltage.

(Means for Solving the Problems) The vertical MOS field effect transistor according to the present invention has a first
A conductive type substrate has a drain of the first conductive type in one main part thereof, a channel region arranged in a matrix in the other main part, and a source of the first conductive type in this channel region, and This vertical MOS field effect transistor has a gate on the substrate surface between the channels, and a region of the second conductivity type is provided in the region where the electric field is concentrated.

(Function) The region of the second conductivity type formed according to the present invention forms a predetermined electric field in the opposite direction to the electric field in the region where the electric field is concentrated, thereby making the spread of the depletion layer almost constant.

(Embodiment) FIG. 1 shows an embodiment of the present invention. In the figure, 1
8 show the same parts as in FIG. 10 is a single-layer region as a region of the second conductivity type, which is an electric field concentration region, that is, each p
It is formed at a position equidistant from the channel region 3, and generates a predetermined electric field in the opposite direction to the electric field.

Since the vertical MOS field effect transistor of this embodiment has a structure in which the 9-layer region 10 is formed at a position equidistant from each p-channel region 3, the electric field near this pMIJ region 10 is generated by the 9-layer region 10. canceled by the electric field, the first
As shown by the dashed line in the figure (C), the spread of the depletion layer becomes almost constant.

(Effects of the Invention) As explained above, according to the present invention, since a predetermined electric field is generated in the electric field concentration region in the opposite direction to the electric field, the spread of the depletion layer becomes almost constant and the This has the advantage that a vertical MOS field effect transistor with high breakdown voltage can be obtained.

[Brief explanation of the drawing]

1M is a diagram showing an embodiment of the present invention, and FIG. 1(a)
is a partially cutaway view of a vertical MOS field effect transistor, FIG. 1(b) is a cross-sectional view taken along the line A, -A shown in FIG. 1(a),
FIG. 1(C) is a sectional view taken along the line B and -B shown in FIG. 1(a). Figure 2 shows a conventional vertical MOS field effect transistor; Figure 2(a) is a partially cutaway view;
b) is a sectional view taken along line A2-A2 shown in FIG. 2(a), and FIG. 2(C) is a sectional view taken along line B2-82 shown in FIG. 2(a). In the figure, 1 is a mouth-shaped substrate, 2 is an n-tren region, 3 is a P-channel region, 4 is an n-source region, 6 is a gate electrode, and 10 is a pH region. Show parts.

Claims (1)

[Claims] A drain of the first conductivity type is provided on one main surface of the first conductivity type substrate,
A vertical MOS electric field having a second conductivity type channel region arranged in a matrix on the other main surface, a first conductivity type source within the channel region, and a gate on the substrate surface between the channels. A vertical MOS field effect transistor characterized in that the effect transistor includes a region of a second conductivity type in a region where an electric field is concentrated.