JPS6325426B2 - - Google Patents

Description

[Detailed description of the invention] The present invention relates to a PCM signal processing device.

As an example of a PCM signal recording and reproducing device, a PCM signal is converted into a signal format similar to a television signal, and a VTR (video tape recorder) is used.
Devices that record and reproduce PCM signals are known.
In FIG. 1, 1 indicates a VTR, and 2 indicates a PCM signal processing device having an adapter configuration. VTR
Reference numeral 1 is, for example, a helical scan type having two rotating heads, and supplies a video signal from a video input terminal 3 to a rotating head (not shown) via a recording system 4, and records it on a magnetic tape. , a reproduction signal from the magnetic tape is supplied to a reproduction system 5, and a reproduction video signal is generated at a video output terminal 8 via one input terminal 7a and an output terminal 7c of a changeover switch 6. The selector switch 6 connects the input terminal 7a and the output terminal 7c only during playback, and connects the output terminal 7 during other recording and stop times.
c is connected to the other input terminal 7b,
It is switched in relation to the operating state of the VTR1. The other input terminal 7b of this switch 6 is connected to the video input terminal 3.

The PCM signal processing device 2 includes a video output end 9 and a video input end 10 connected to the video input end 3 and video output end 8 of the VTR 1, respectively. An A/D converter 13, an encoder 14, and a video amplifier 15 are inserted between the analog input terminal 11 and the video output terminal 9, and a synchronous separation circuit is inserted between the video input terminal 10 and the analog output terminal 12. circuit 1
6, a decoder 17, and a D/A converter 18 are inserted. Amplifier 1 for analog output terminal 12
A monitor speaker 20 is connected via 9. Actually, the stereo audio signal
Since it performs PCM modulation and PCM demodulation, A/D converter 1
3 and a D/A converter 18.
PCM modulators and PCM demodulators are provided for two channels.

The encoder 14 relates to the left and right channels.
Converts PCM data to an error-correctable code structure,
It also performs time axis compression processing to form a data pause period corresponding to a vertical blanking period in a video signal, and also performs processing to add a synchronization signal corresponding to a vertical synchronization signal and a horizontal synchronization signal. In this example, a parity code and interleave are used as error-correctable code structures, as will be described later. The decoder 17 performs error correction processing and time axis expansion processing.
Deinterleaving is performed for error correction.

FIG. 2 shows an example of the encoder 14, in which PCM data regarding the stereo signals of the left and right channels is supplied from the input end 21, and is supplied to the distributor 22, and the PCM data regarding the left channel and right channel are supplied.
The PCM data series is divided into SL and SR. The PCM data for the left channel is, for example, a series of 1 word Li with a length of 14 bits, and similarly the PCM data for the right channel is a series of 1 word Ri with a length of 14 bits. One word each is taken out from the PCM data series of these left and right channels and supplied to the adder 23 (mod.2) to form a parity data series SP consisting of a 14-bit parity word Pi (=LiRi). Ru. FIG. 4A emerges from the divider 22 and adder 23.
It shows the series of PCM data and parity data. These three sequences are interleaved by being delayed for different times. The left channel PCM data series is supplied as is to the synthesizer 25, and the right channel PCM data series is supplied as is to the synthesizer 25.
The data series is sent to the synthesizer 2 via the delay circuit 24a.
5, and the parity data series is supplied to a combiner 25 via a delay circuit 24b. The delay amounts of the delay circuits 24a and 24b are selected to have a difference of D and 2D (block time), respectively. As an example (D=2 block time)
Then, the time relationship of each interleaved data series is as shown in FIG. 4B. For each interleaved data sequence, three words occupying the same timing are processed by the CRC generator 26.
CRC code as an error detection code
A CRC code sequence SC consisting of C ₀ , C ₁ , C ₂ . . . is formed. This CRC code sequence SC is also
supplied to CRC (Cyclic Redundancy)
Check) is a type of error detection using cyclic codes.
Each bit of the code to be detected is used as a coefficient.
The polynomial on GF2 is divided by the generator polynomial, the remainder is added to the transmission code as a CRC code, and on the receiving (or reproducing) side, the presence or absence of errors is checked by dividing the transmission code and CRC code by the generator polynomial. It is.

The output terminal 27 of the synthesizer 25 has a PCM serialized for each transmission block as shown in FIG. 4C.
A signal (including a parity code for error correction and a CRC code for error detection) appears, and although not shown,
A synchronization signal similar to a television signal is added in a synchronization mixing circuit. A data pause period corresponding to the vertical blanking period in a television signal is provided, but even if both the time axis compression and the delay for the above-mentioned interleaving processing are performed using RAM (random access memory). good.

Further, the decoder 17 is configured as shown in FIG. PCM data from the synchronization separation circuit 16 is supplied from an input terminal 28 to a distributor 29, and each transmission block is divided into four sequences SL, SR ₁₁ , SP ₁ and SC. 2 words of PCM for each transmission block
The data, one word of parity data, and the CRC code are supplied to the CRC checker 30, which detects the presence or absence of errors in the transmission block.The one-bit pointer that is the result of the detection is sent to each word as shown in the path shown by the broken line. It is added every time. Distribution circuit 2
The time relationship of the reproduced data on the output side of 9 is similar to that shown in FIG.
The playback PCM data for the right channel is delayed by D (block time). The playback parity data is
Due to this deinterleaving, the time relationship of the reproduced data at the input side of the error correction circuit 32 becomes similar to that shown in FIG. 4A. In the error correction circuit 32, a syndrome is formed and a correction operation based on the syndrome is performed. Considering two words Li and Ri that form a certain parity word Pi,
If Pi is correct, these two words Li, Ri
If only one word is incorrect, the error can be corrected using the syndrome. The data regarding the left and right channels from the error correction circuit 32 is supplied to the correction circuit 33, and the output of the correction circuit 33 is supplied to the synthesis circuit 34, where it is made into one channel and guided to the output terminal 35.

Interleaving and deinterleaving have the advantage of minimizing the occurrence of two-word errors, and are effective against burst errors.
As an example, regarding the reproduced data, [L ₀ ,
Two consecutive sequences of R _-2 , P _-4 ] and [L ₁ , R _-1 , P _-3 ]
If one transmission block is detected as erroneous by the CRC codes C ₀ and C ₁ , then as a result of the deinterleaving process, these erroneous words are dispersed and, assuming there are no other errors, they are all 1. It becomes possible to correct a word error. Second
The burst correctable length when using the encoder and decoder shown in FIG. 3 and FIG. 3, respectively, is D (block time). In addition, the correction circuit 33 corrects erroneous words that cannot be corrected in the error correction circuit 32. The correction circuit 33 can correct erroneous words that cannot be corrected in the error correction circuit 32. There is a previous value hold that uses the level of the correctly located word as is.

As mentioned above, VTR1 and PCM signal processing device 2
When operating in combination with
When the VTR 1 is stopped from the state in which the reproduced PCM signal from the VTR 1 is being supplied to the PCM signal processing device 2, the connection state of the changeover switch 6 is automatically changed, and its input terminal 7b and output terminal 7c are connected. Ru. For example, if a microphone output is supplied to the analog input terminal 11 because the A/D converter 13, encoder 14, and video amplifier 15 of the PCM signal processing device 2 are operating, this microphone output is PCM-modulated. and appears in the digital output terminal 9 in a regular signal form, so after the terminals 7b and 7c of the changeover switch 6 are connected,
This disparate video signal appears at the video output terminal 8.
It is supplied to the video input terminal 10 of the PCM signal processing device 2. Due to the switching transient of the changeover switch 6, different types of PCM signals are connected after a signal loss time. When the signals are deinterleaved in the decoder, a section in which different types of PCM signals coexist is generated. Therefore, if an error correction operation using different types of PCM data is performed within this section, abnormal data that is completely different from the original PCM data may be generated, which may result in the generation of unpleasant noises. There is.

Further, if the video signal played by the VTR 1 is #1 and the video signal generated via the encoder 14 is #2, the phase relationship between the two video signals is not regulated in any way, so
Abnormal data caused by this also occurs.

The occurrence of abnormal data due to the use of interleaving and deinterleaving will be explained with reference to FIGS. 5 and 6. Fifth
Figure A shows the #1 video signal played back by the VTR 1, and Figure B shows the #2 video signal generated via the encoder 14 of the PCM signal processing device 2.
shows the video signal. The signal format of these video signals is a data pause period TBL that includes a vertical synchronizing signal VD, equalization pulse (not shown), pilot signal PS (shown as a solid shaded area), etc. in one field (1V), and data. This includes the period TDT. However, the phases of video signals #1 and #2 are not synchronized as shown. pilot signal
PS indicates the start of the data period TDT in one field, and is inserted in one horizontal interval in the same signal form as the data shown in FIG. 4C.

Now, when the changeover switch 6 is switched at the timing shown by _t0 , the video signal shown in FIG. 5C is supplied to the video input terminal 10 of the PCM signal processing device 2. When the delay circuits 31a and 31b for deinterleaving are configured with RAM, the write gate pulse WGP as shown in FIG. 5D is supplied to this RAM, and the input PCM
Data is written sequentially. And from RAM
PCM data is read out sequentially, and in that case, deinterleaving is also performed by performing predetermined address control. write gate pulse
WGP becomes "1" corresponding to the data period TDT, and becomes "0" corresponding to the data pause period TBL. This write gate pulse WGP is
It is formed based on a horizontal synchronization signal and a vertical synchronization signal separated from the input video signal. If a correct synchronization signal cannot be extracted due to dropout, an equivalent signal is generated. Therefore, t ₀
Even if the changeover switch ₆ is switched at
Or it becomes "1" and synchronizes with the video signal #2 after the timing indicated by _t1 .

The write gate pulse WGP shown in FIG. 5D
As a result, the portions S ₁ to _{S 5} indicated by the dashed hatched areas in FIGS. B and C are written to the RAM. That is, there is a lack of signals between S ₁ and S ₂ as well as between S ₄ and S ₅ , and along with this, the data pause period S ₃ (including the pilot signal PS) is also written to the RAM. It turns out.

Similarly to FIG. 4B, if the above-mentioned signal relationship is shown as each data series before being deinterleaved, the 6th
The result is as shown in Figure A. In the same figure, [S ₁ ] ~
The part [S ₅ ] is included in the parts S ₁ to S ₅ ,
It shows what is processed as each data series. Similarly, the data of the pilot signal PS [PS]
It is expressed as After deinterleaving, each data sequence SP ₁ , SR ₁₁₁ , SL ₁₁ becomes as shown in FIG. 6B. When switch 6 is switched and the connection point of different types of PCM signals is indicated as t ₀ ,
The interval TD ₁ from t ₀ to 2D is an interval in which different types of PCM data included in the video signals #1 and #2 are mixed, and within this interval, the signal disappears due to the transient of switch 6, etc. This may cause abnormal noise to occur as a result of error correction. Also,
[S ₁ ] and [S ₂ ] parts (data) overlap
There is also a possibility that abnormal noise may occur in the 2D section TD ₂ as well. In other words, the data of [S ₁ ] and [S ₂ ] are both #2
was included in the video signal of S ₁ and
During _S2 , the write gate pulse WGP is "0", so data during that period is not written to the RAM, resulting in a lack of signal and loss of data continuity.
Therefore, there is a risk that abnormal noise will occur in this portion _TD2 . This holds true in exactly the same way for the section TD ₆ where the parts [S ₄ ] and [S ₅ ] overlap.
Further, the [S ₂ ] and [S ₃ ] portions also overlap over a 2D section as shown by TD ₃ . but,
[S ₃ ] originally corresponds to the data idle period TBL, and except for the pilot signal PS,
As a result of the CRC check, it was naturally detected as an error,
However, in the case of an error only in the parity data, no abnormal noise is generated because error correction is not performed.

Since the pilot signal PS has the same signal form as the data, if no error occurs during transmission, it will be detected as correct as a result of the CRC check. Therefore, the data [PS] of the pilot signal PS is included in the parity data series SP ₁ .
There is no problem in the TD ₄ section, but in the TD ₅ section where this is included as the PCM data series SR ₁₁₁ or SL ₁₁ , this data [PS] may be used for error correction or correction. Since the pilot signal PS has a predetermined bit pattern with no correlation with the PCM data, if such data [PS] is used for error correction or correction, there is a risk that abnormal noise will occur.

In the present invention, abnormal data is generated as a result of error correction or correction after being deinterleaved by asynchronously connecting different types of PCM signals having a data pause period at a predetermined cycle as described above. This is designed to prevent such occurrences (this applies to sections TD ₂ , TD ₃ , and TD ₆ where there is a risk of such occurrence).

An embodiment of the present invention will be described below with reference to FIG. In this embodiment, four detection circuits 36, 37, 38, and 39 are provided as shown surrounded by broken lines in order to prevent abnormal data from occurring due to various types of errors. Since it takes a predetermined amount of time for the detection circuits 36 to 39 to detect the occurrence of abnormal data, the data series SL, SR ₁₁ and SP ₁ generated from the distribution circuit 29 are processed by the buffer memories 40a, 40b and 40c, respectively. D
, and then deinterleave processing is performed. This buffer memory 40
a, 40b, 40c and the deinterleaving delay circuits 31a, 31b are constituted by RAM, and writing or reading of data to or from this RAM is controlled by a timing pulse generated by a timing pulse generator 41. be done. The timing pulse generator 41 generates pulses necessary for the decoder 17 and the D/A converter 18, such as clock pulses and various control pulses, based on the horizontal synchronization signal and vertical synchronization signal separated by the synchronization separation circuit 16. . Here, only the write gate pulse WGP relevant to the gist of the present invention is considered.

Also, the output (pointer) of the CRC checker 30
is a pulse-like signal that is generated at the end of one block of data period and becomes "1" when an error is detected and "0" otherwise. The output of this CRC checker 30 is supplied to an OR gate 42 together with a pseudo pointer PP generated as described later, and is sent to buffer memories 40a to 40.
c is appended to each corresponding word of data at the output of c. After being deinterleaved, the pointer becomes "0" (if there is no error) or "1" (if there is an error) for one word period of each corresponding word.

Deinterleaved data series SL ₁₁ ,
SR ₁₁₁ and SP ₁ are supplied to the muting circuit 43. The muting circuit 43 includes a monostable multivibrator (hereinafter abbreviated as monomulti) 4
The muting signal obtained at the output of 4 is “1”
This is to cut off data transmission in the case of In the case of this interruption, the pointer associated with the data is forcibly changed to "1". An error correction circuit 32 is provided after the muting circuit 43. The syndrome forming circuit 45 supplies the three words obtained from each data series to a (mod. 2) adder, and supplies the syndrome obtained at its output to the error correction circuit 32. Therefore, one word of the syndrome has the same number of bits as one word of data, and if there is no error, all the bits will be "0", and if there is an error, at least one bit will be "1". ” becomes. A syndrome signal SS is formed which becomes "1" when even one bit of this syndrome becomes "1".

First, the detection circuit 36 detects that there is a signal considered to be a data pause period in the data interval (WGP="1") and generates a detection signal _Pm1 . During the data pause period TBL, vertical synchronization signal VD, equalization pulse EQ, pilot signal PS
are inserted, detection circuits 46, 47, and 48 are provided to detect these signals from the video signal from the video input terminal 10, and each detection output that becomes "1" at the time of detection is supplied to the AND gate 49. has been done. The detection circuits 46, 47, and 48 are provided to prevent a simple signal loss period from being detected as a data pause period.
Instead of ANDing the three detection outputs, a configuration may be adopted in which two of the detection outputs are determined to be "1" as a data pause period. The output of the AND gate 49 and the write gate pulse WGP are supplied to the AND gate 50, and the detection signal Pm ₁ generated at the output of the AND gate 50 is supplied to the OR gate 51. The detection signal Pm ₁ of this detection circuit 36 is
“1” when detecting the S ₃ part in Figure 5
becomes.

Next, the detection circuit 37 detects that data is taken out during the data pause period (WGP="0") and generates a detection signal _Pm2 .
The pointer appearing from CRC checker 30 is “0”
This is only the data or pilot signal PS that has not caused an error during transmission. Therefore, the pointer is inverted by the inverter 52 and the pointer is changed to the counter 5.
3, and detects two or more consecutive numbers, and at that time, the detection output becomes "1".
WGP is supplied to the AND gate 54, and the detection signal Pm ₂ generated at the output of the AND gate 54 is supplied to the OR gate 51. The detection signal Pm ₂ formed by this detection circuit 37 is different from the signal S ₁ in FIG.
It becomes "1" when detecting a lack of data between S2 and _S2 .

The monomulti 44 is triggered by the output of the OR gate 51. mono multi 4
The delay time associated with the time constant of 4 is the detection signal Pm ₁
Alternatively, the muting signal is selected to be "1" for a predetermined period after Pm ₂ becomes "1". Therefore, in the case shown in FIG. 5, the detection signal Pm ₂ becomes "1" a little after the signal S ₁ , and
From this rising edge, a muting signal that becomes "1" is generated from the monomulti 44, and the muting circuit 43 operates to interrupt data transmission. Therefore, it is possible to prevent abnormal data from occurring in the section TD ₂ in FIG. 6B. Also,
The detection signal Pm ₁ becomes "1" within the portion S ₃ corresponding to the data pause section in the case of FIG. 5.
As explained in FIG. 6B above, TD ₃ ,
In the section of TD ₄ , there is no possibility that abnormal data will occur, so there is no need to provide the detection circuit 36. However, in cases where the unit delay amount D of interleaving is quite large, there is a possibility that a section in which a one-word error occurs after deinterleaving occurs, so this is necessary in such a case. It is necessary to mute the section of TD ₅ where the data [PS] corresponding to the pilot signal PS may be used for error correction or correction. Another case where the detection circuit 36 is effective is when the error correction code is capable of correcting a 2-word error, as will be described later. Furthermore, even slightly after signal S ₄ ,
The detection signal Pm ₂ becomes "1", and in Fig. 6B
It is possible to prevent abnormal data from occurring in the TD ₆ section.

Further, the detection circuit 38 is intended to prevent abnormal data from being generated due to a signal error occurring in the vicinity of the connection position t ₀ of different types of video signals. If the period of this signal error is d, then the error contained in the #1 and #2 video signals may be due to burst errors in the case of (D≦d<2D) or random errors that occur before and after the connection point. A correction operation is performed using the corrected PCM data, which may result in abnormal data. A similar possibility exists when a burst error (D>d) occurs after the connection point t ₀ , but this is prevented by the other detection circuit 39 .

The detection circuit 39 receives a NOR gate 55 to which a pointer (this signal continues for one word period) attached to each data series is supplied, a detection output from the NOR gate 55, and a syndrome signal.
SS is supplied to an AND gate 56, and a monomulti 5 is triggered by the output of the AND gate 56.
It consists of 7. A detection signal Pc ₁ is generated from this monomulti 57 and supplied to an OR gate 58 . The output of the OR gate 58 is supplied to the error correction circuit 32 and the correction circuit 33. During the period in which the output of the OR gate 58 is "1", the error correction operation is prohibited and the correction operation is performed. If a data error of length (D>d) occurs after the connection point _t0 , a one-word error may occur in a part of the section indicated by TD ₁ in FIG. 6B,
In this case, an error correction operation using different types of PCM data may be performed, and as a result, abnormal data may occur. However, at the time before this case, since the PCM data is of a different type, the syndrome signal SS becomes "1" and all three word pointers are "0", so the NOR gate 5
Since there is a state in which the detection output from the AND gate 56 becomes "1", the output of the AND gate 56 becomes "1", and the detection signal becomes "1" in the approximately 2D section TD ₁ .
Pc ₁ occurs. In the interval in which this detection signal Pc ₁ is "1", the error correction operation is prohibited and the correction operation is performed.
Abnormal data generation is prevented.

According to the detection circuit 39, when a data error of length (D≦d<2D) occurs, the detection signal is
SD remains “0” and the possibility of abnormal data occurring cannot be detected. For this purpose, a detection circuit 38 is provided. A re-trigger type mono multi 59 triggered by the output of the CRC checker 30, an AND gate 60 for giving the output of the CRC checker 30 to the counter 61 in an interval where the output of the mono multi 59 is "1", and a mono multi 62. The detection circuit 38 is constructed by the following. The counter 61 detects that D outputs (indicating errors) from the CRC checker 30 are generated continuously and generates a carry output. Ru. The monomulti 62 is triggered by the carry output of the counter 61, and the detection signal Pc ₂ becomes "1" in the approximately 2D section. This detection signal Pc ₂ is supplied to the OR gate 58, and the same control is performed according to the detection signal Pc ₁ .

The above-mentioned detection circuit 36 uses data [PS] corresponding to the pilot signal PS for error correction or correction, thereby preventing abnormal data from occurring. However, due to signal loss, there is a possibility that the data pause period TBL cannot be detected from the video signal supplied to the video input terminal 10. This is especially likely when the connection point t ₀ is located immediately before or within the data pause section TBL. As a countermeasure against such a case, when the output of the OR gate 58 is "1" and the pilot signal PS is detected by the detection circuit 48 in a state where a correction operation is performed, the output of the AND gate 6 is
Set the output of 3 to “1” and use this as the pseudo pointer PP
The signal is supplied to the OR gate 42 as a signal. Therefore, the data of each channel appearing at the output of buffer memories 40a, 40b, and 40c are all forced to be error words. Depending on the delay necessary to detect the pilot signal PS, the delay caused in the distribution circuit 29, etc., the buffer memories 40a, 40b, 40
A pseudo pointer PP may be added on the input side of c. In this way, even if the detection circuit 36
Even if a detection error occurs, it is possible to reliably prevent error correction or correction from being performed using the data of the pilot signal PS.

As understood from the description of one embodiment above,
According to the present invention, different types of PCM signals are connected asynchronously, thereby preventing continuity of PCM data from being lost and abnormal data from occurring as a result of error correction. Unlike the present invention, it is also possible to detect that the video signals are asynchronously connected by detecting the vertical synchronization signal VD in the video signal supplied to the video input terminal. However, the vertical synchronization signal VD is 1
Because it is inserted at field intervals, in the worst case, one field (=1/60 second) may elapse before it is detected.In the example in Figure 6B, TD ₂
Abnormal data occurs in the interval. There is also a possibility that the vertical synchronization signal VD cannot be detected due to signal loss. According to the present invention, there is no such drawback and generation of abnormal data can be reliably prevented. Furthermore, if the VTR system control signal and the like can be separately supplied to the PCM processing device, it is possible to similarly prevent the occurrence of abnormal noise. However, the need for such a separate signal transmission line causes disadvantages such as detracting from the advantage of being able to easily add a PCM signal processing device to a VTR using an adapter configuration. According to the present invention, there is an advantage that generation of abnormal noise can be prevented using only the reproduced PCM signal.

Another encoding method to which the present invention can be applied will be explained with reference to FIG. 8 and subsequent figures. FIG. 8 shows an encoder, which is distributed by a distribution circuit 22a into PCM data series SL and SR of left and right channels,
The left and right channels are divided into a total of six channels, three channels each, by the distribution circuit 22b. For example, the PCM data series SL that continues L _-2 , L _-1 , L ₀ , L ₁ , L ₂ , L ₃ ... and R _-2 , R _-1 , R ₀ , R ₁ ,
The PCM data series SR that continues with R ₂ , R ₃ , etc. is
(L _-2 , L ₁ , L ₄ ...), the PCM data series SL ₁ of the first channel, and (R _-2 , R ₁ , R ₄ ...)
PCM data series of the second channel followed by
SR ₁ , PCM data series SL ₂ of the third channel following (L _-1 , L ₂ , L ₅ ...), and (R _-1 , R ₂ ,
PCM data series SR ₂ of the fourth channel followed by R ₅ ...) and the fifth channel followed by (L ₀ , L ₃ , L ₆ ...)
PCM data series SL ₃ of the th channel,
(R ₀ , R ₃ , R _{6 .} . . ) and the subsequent PCM data series SR ₃ of the sixth channel.

One word of the PCM data sequence of each channel is supplied to the (mod.2) adder 23 to form the first parity data sequence SP, and the adjacent encoder 64
A second parity data series SQ is formed by supplying each word of the PCM data series.

For other channels except PCM data series SL ₁
The PCM data series SR ₁ , SL ₂ , SR ₂ , SL ₃ , SR ₃ are supplied to delay circuits 24a to 24e, respectively, the first parity signal series SP is supplied to the delay circuit 24f, and the second parity signal series SQ is the delay circuit 24
g. The delay circuits 24a to 24g are
The delay circuits 24a to 24g are for temporally interleaving the PCM data series and the first and second parity data series, and when the unit delay amount is D (block time), the delay circuits 24a to 24g are D and 2D, respectively. ,
It is said to have a delay amount of 3D, 4D, 5D, 6D, and 7D (block time). Delay circuits 24a-2
PCM data series SR ₁₁ delayed from each of 4e,
SL ₁₂ , SR ₁₂ , SL ₁₃ , SR ₁₃ occur, and the delay circuit 24
Delayed parity data sequences SP ₁ and SQ ₁ result from f and 24g, respectively. The PCM data series for 6 channels obtained in this way SL ₁ ~
Eight words are extracted from SR ₁₃ and parity data sequences SP ₁ and SQ ₁ and supplied to a CRC generator 26 to generate a CRC code for these eight words, and form a CRC code sequence SC consisting of these CRC codes.

The above PCM data series SL ₁ to SR ₁₃ , parity data series SP ₁ , SQ ₁ , and CRC code series SC are supplied to the synthesis circuit 25 to form a one-channel PCM signal series, which is further illustrated in the figure. The signal is also supplied to the time base compression circuit. At the output terminal of the time axis compression circuit, a signal sequence having a data pause period corresponding to the period in which the synchronization signal is added appears. In this case, six words of PCM data, two words of parity data, and a CRC code are located within one horizontal section. As an example, each delay circuit 2
PCM of (R ₁ , L ₂ , R ₂ , L ₃ , R ₃ ) in 4a to 24g
At the timing when the data and the parity data of P ₁ and Q ₁ are supplied, (R _1-3d , L _2-6d , R _2-9d , L _3-12d , R _{3- 15d} )
PCM data and parity data of P _1-18d and Q _1-21d are generated at the outputs of delay circuits 24a-24g.
The output signals of these delay circuits 24a to 24g and
A CRC code _C1 for a total of 8 words including _L1 is formed.

The PCM signal generated by the encoder mentioned above is
As shown in FIG.
Data, two words of parity data, and a CRC code are arranged in sequence. In this example,
One word is 14 bits long.

FIG. 10B shows a signal waveform recorded and reproduced by a VTR.
The data 66 and the white level reference signal 67 shown in the figure are inserted into the waveform.

FIG. 9 shows a decoder corresponding to the above-mentioned encoder, in which data from the input terminal 28 is sent to a distribution circuit 29 into a 6-channel PCM data series SL ₁ , SR ₁₁ , SL ₁₂ , SR ₁₂ , SL ₁₃ ,SR ₁₃ ,
It is divided into SP ₁ , SQ ₁ and CRC code series SC, and error detection is performed by CRC checker 30 for each transmission block, and the detection result (pointer) is added to each word and sent to delay circuits 31a to 31g. Deinterleaving processing is performed using . After this deinterleaving, an error correction circuit 32 performs error correction, a correction circuit 33 further corrects the PCM data series, which is returned to one channel by a synthesis circuit 34, and appears at an output terminal 35.

Error correction in the above example will be explained. As an example, from the distribution circuit 22b, L ₁ , R ₁ , L ₂ , R ₂ , L ₃ ,
When 6 words of R ₃ are generated, adder 23
The first parity data P ₁ generated from is P ₁ = L ₁ R ₁ L ₂ R ₂ L ₃ R ₃ , and the second parity data Q ₁ is Q ₁ = T ⁶ L ₁ T ⁵ R ₁ T ⁴ L ₂ T ³ R ₂ T ² L ₃ TR ₃ . The generation matrix T is formed by a d-order generation polynomial G(x) such that the same one does not appear in each of T, T ² , T ³ , T ⁴ , T ⁵ , and T ⁶ in the above equation. be.

Further, in the error correction circuit 32 of the decoder, the first
forming a syndrome based on parity data and a syndrome based on second parity data,
Error correction is performed by using syndromes based on the first and second parity data. By identifying the erroneous word using CRC, it is also possible to correct two-word errors within the same block. Therefore, the burst correctable length when using the encoder and decoder shown in FIGS. 8 and 9 is 2D (block time).

As described above, the present invention can also be applied to an encoding method that uses the first and second parity signals in addition to dividing a PCM data sequence into six channels, so that different types of PCM signals can be This has advantages such as being able to reliably prevent abnormal data from occurring due to asynchronous connections.

Note that the present invention may be applied to other methods that use a parity check as an error detection code or a full addition code as an error correction code.

[Brief explanation of drawings]

FIG. 1 is an overall block diagram of a PCM signal processing device to which the present invention can be applied, FIGS. 2 and 3 are block diagrams of an example of its encoder and decoder, and FIG. 4 is used to explain the operation of the encoder and decoder. A schematic diagram, FIGS. 5 and 6 are time charts used to explain the case where different types of PCM signals are connected asynchronously, FIG. 7 is a block diagram of an embodiment of the present invention, and FIGS. 8 and 9 Figure 1 is a block diagram of another example of an encoder and decoder to which the present invention can be applied.
FIG. 0 is a schematic diagram showing transmission waveforms of another example of this encoder and decoder. 1 is a VTR, 2 is a PCM signal processing device, 6 is a changeover switch, 14 is an encoder, 17 is a decoder,
23 is a (mod.2) adder, 24a to 24g are delay circuits for interleaving, 26 is a CRC generator,
30 is a CRC checker, 31a to 31g are delay circuits for deinterleaving, 32 is an error correction circuit,
33 is a correction circuit, 36, 37, 38, 39 are detection circuits, and 43 is a muting circuit.

Claims (1)

[Claims] 1 Interleave processing is performed to delay PCM data and an error correction code for this PCM data by different times, and the blocks are formed and transmitted. This transmission signal has a data pause section at each predetermined period, and is difficult to receive (or reproduce). ) side performs error detection, performs deinterleaving processing to cancel the above-mentioned delay, and performs error correction. In the PCM signal processing device, a second different type of PCM signal is connected to the first PCM signal and asynchronously supplied. On the receiving (or reproducing) side, there is a memory for performing deinterleaving processing, a write timing signal forming means for forming a write timing signal for controlling writing of input PCM data to the memory, and a means for detecting errors in each block. an error detection means for detecting; a first logic means to which the output of the error detection means and the output of the write timing signal forming means are supplied; and a data pause period for generating a signal indicating a pause period of the input PCM signal. a signal generating means; a second logic means to which the output of the write timing signal forming means and the output of the data pause period signal generating means are supplied; and error correction according to the outputs of the first and second logic means. 1. A PCM signal processing device which prevents abnormal data from occurring due to asynchronous connection of first and second PCM signals.