JPS63254544A - Control system for address conversion - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to an address translation control method for a computer using a virtual memory method, and in particular a high-speed memory (address translation buffer) for storing previously processed contents of address translation. ) assignments relate to control methods.

[Conventional technology]

In electronic computers using virtual memory, a high-speed memory is generally prepared in the processor, and logical address-real address pairs obtained by previous address conversion processing are registered in the high-speed memory. As for addresses, by reading real addresses from the high-speed memory, the speed of address conversion from virtual addresses to real addresses is increased.

This high-speed memory is called an address translation buffer.

As highly integrated LSIs are used in electronic computers, highly integrated memory elements are also used for high-speed memories used in address translation buffers, and address translation buffers are increasing in capacity with each development. However, even if the capacity of the address translation buffer is increased beyond a certain level, the information registered in the address translation buffer will be replaced with information for the new task when tasks are switched, so the address translation buffer It can be said that the performance improvement effect due to capacity increase has reached saturation.

On the other hand, services can be provided by installing multiple OS (operating systems) on one machine.

The use of electronic computers is becoming more and more sophisticated.

Such services are also required to have higher performance.
Various improvements have also been made to address translation buffers.

When multiple OSes are installed on one machine, the machine divides machine resources into unit time and allocates them to each OS sequentially.In other words, from the perspective of one machine, various OSs
The cars will be replaced and the cars will be switched and run. At this time, in the address translation buffer, if no measures have been taken to speed up the situation, logical address a is mapped to real address b in IOS, and other
In S, logical address a is mapped to real address C, so in order to remove logical contradictions, O
It is necessary to completely clear the address translation buffer every time S is switched. Conventionally, in order to avoid this situation, each OS identifier (ID
), and even if the logical address is the same, if the ID is different, the entry is controlled to be unusable.

[Problem that the invention seeks to solve]

Even when the above control method is adopted, for example, when running 081, the pair of logical address and real address registered in the address translation buffer (in the field of current medium and large machines, the same "address translation buffer index address" is 2 When the OS is switched and OS2 is running, if two or more identical "address translation buffer index addresses" are detected and registered in the address translation buffer, it is the previous running OS. The OSI address translation information is replaced with new OS information on the address translation buffer, and the information is erased from the buffer.

In addition, when providing services using multiple OSs, for example, one
There is a demand for high performance processing for only OS 08, or for performing priority control in terms of performance for each of multiple OSs. In this case, in the conventional control method described above, for example, if OSI is the priority OS, when switching to OS2, the address translation information of 081 is evicted from the address translation buffer, and the next time the OS is dispatched to 081 again, the valid address The conversion information is not present in the buffer, and a new registration procedure (segment table, page table index) must be performed again, resulting in a large performance overhead. That is, even if the address translation information of the priority OS is switched to another OS, it is desirable that the previous information remain in the buffer when the priority OS is dispatched again.

In view of the above situation, an object of the present invention is to give priority to allocation to address translation buffers when a plurality of program modules or OSs are running, so that address translation information of a specific OS, etc. The object of the present invention is to provide a flexible address translation control system by allowing the address translation buffer to remain on the address translation buffer when the OS or the like is switched and dispatched again to the specific OS or the like.

[Means and effects for solving the problem] The present invention divides an address translation buffer into a plurality of areas (sections), and when a plurality of program modules or OSs run, at least one area is divided into sections. Allocated preferentially to store module or OS address translation information.

When writing to or reading from the address translation buffer, the section number of the currently running program module or OS is held, and only that section is accessed without disturbing other sections. As a result, when switching to another program module or OS and dispatching to a specific program module or OS again, the address translation information remains on the address translation buffer.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows a configuration diagram of an embodiment of the present invention. In FIG. 1, the address translation buffer 3 is physically divided into a plurality of sections #0 to #n, each section consisting of a plurality of entries, each storing address translation information. Priority is given to the allocation of each section #0 to #n of this address translation buffer 3, and a certain program module or OS is registered in only one section, even if the processing is switched to another program module or OS. , the section can be accessed by other program modules or O
To prevent the adverse effects of S, or to minimize the effects. A section allocation table 5 holds the correspondence between each section #0 to #n of the address translation buffer 3 and a program module or OS.

First, before operating the processor, the section allocation table 5 is initialized from outside the processor (for example, from a service processor or the like). This initialization only determines the initial values, and when necessary, the contents of the section allocation table 5 can be changed to the line 401. It is rewritten via the update circuit 4. This section assignment table 5 has the configuration shown in FIG. 2(a), and the contents of the section assignment table 5 are set, for example, as shown in FIG. 2(b). In FIG. 2(b), section 0 is assigned top priority to the program module or OS with ID number 1, and section 1 is assigned with ID number 2.
Section 2 is shared by ID numbers 3 and 6.8, and section 3 is shared by ID numbers 4 and 7.9 to F.

When running a certain program module, before running the program module or when running a certain OS, the OS identifier (
ID) is loaded into ID register 2 with the instruction. ID
The contents of register 2 are decoded by decoder 51 (Fig. 2), and the pre-stored section number is read from the entry corresponding to the ID in section allocation table 5, and the result (current section number) is It is held in the section number holding register 6.

From the next command onwards, only the command corresponding to the ID will run. The logical address indicated by the next instruction is logical address register 1
is set to Based on the contents of the section number holding register 6 and the contents of the logical address register 1, the section indexing circuit 7 indexes the entry within the determined section number on the address conversion buffer 3.

FIG. 3 shows details of the section index circuit 7.

FIG. 3 shows an example of a circuit designed to easily switch between a mode in which the address translation buffer 3 is used by dividing it into multiple sections (Mode A) and a mode in which it is used without being divided into sections (A). .

In the case of mode A, AND circuits 711, 712° 713
etc. and OR circuits 721, 722, 723, etc., the contents of the section number holding register 6 in FIG.
．． Only the section number decoded via the decoder 61 is valid.

For example, when section number #0 is specified in register 6, only the output of OR circuit 721 is "1'; (722, 7
The output of 23 becomes "0"), and the AND circuits 731 and 74
1,751, the corresponding entry number in section 0 is specified by the decoding result of the lower 14 decoders 17 of the page number of the logical address register 1,
Read out. On the other hand, in the case of mode A, instead of the contents of register 6, the lower 12 segment numbers of logical address register 1 are decoded by decoder 16, and the AND
Circuits 701, 702, 703. OR circuits 721, 722
, 723, section designation of the address translation buffer 2 is performed. As in mode A, the entry number within the section is specified below the page number of logical address register 1. This mode A is
It is used in cases where it is more effective to use all sections with the same ID.

The data read from the address translation buffer 3 is held in the address translation data register 30, and its ID3
1. The key comparison circuit 8 compares the KEY part 32 of the logical address to see if it is a corresponding logical address. When a match is detected in the key comparison circuit 8, a match signal is sent to the selector 9, and the real page number 33 of the address translation data register 30 is selected and set in the real page register 10. The same applies to the protection bits 34 of the register 30.

FIG. 4 shows details of the key comparison circuit 8. FIG. 4 also shows a circuit configuration for operating in either mode A or mode A. ID3 of address conversion data register 3o
1 is the content of the current ID of ID register 2 and the comparator 80
1 and if they match, the output of the gate circuit 811 becomes II I 11. Further, 323 of the KEY part 32 of the logical address of the register 30 is compared with the upper 13 page numbers of the logical address register 1 by the comparator 804, and if they match, the output of the gate circuit 814 is "1".
becomes. 321 and 322 of the KEY section 32 of the logical address of the register 3o are compared with the segment number 11.12 of the logical address register 1 by comparators 802 and 803, respectively, and the results are output to gate circuits 812 and 813.

In mode A, all bits of the segment number are stored in the address translation buffer 3 and are valid. Therefore, the output of comparator 803 is treated as valid. In mode A, the lower part of the segment number is allocated to the section designation, so the contents of 322 in the address translation buffer 3 are invalid. circuit 82, AND circuit 813. The OR circuit 823 performs these controls. The outputs of the AND circuits 811, 812, 814 and the OR circuit 823 are all ANDed in a circuit 85, and the KE of the ID and logical address is
If the Y parts match, the corresponding logical address is
A match signal is sent from the AND circuit 85 to the selector 9 in FIG. 1, and the actual page number 33 is output.

The method shown in the above embodiment is mode A.As for how to use mode A at present, mode A is a virtual machine (VM) mode in which multiple OSes are run on one machine, and mode A is a one-machine 10S mode. There is a Barθ machine mode that runs in VM mode, and dividing the address translation buffer into multiple sections is effective in VM mode. however,
The method shown here is not only effective for VM Momo, but also for specific program modules (
This is effective when prioritizing tasks (tasks).

Figures 5 and 6 show examples of section allocation for address translation buffers, and Figure 5 shows an example where the number of sections is 2.
In this case, FIG. 6 shows the case where the number of sections is four. LID (one program module or O
If only S) is assigned, the highest priority is assigned, and multiple I
If D is assigned, the priority is low. Further, when the number of IDs is fixed, for example, the method shown in FIG. 6 (3) is advantageous, and when it is variable, the method shown in FIG. 6 (2) is advantageous, and it is significant that this priority order can be changed.

FIG. 7 shows an example of the contribution rate to the instruction execution time with respect to an increase in the number of entries in the address translation buffer. The 7th point is that the contribution rate is low even if there are more than one room.
Figure (2) shows this. Figure 3 (3) shows the following. When using a mixture of osa and os, for example, osa and os often use similar logical addresses.
When it is dispatched to OS゜ and returns to osa again.

Most of the time, valid information remains in the address translation buffer, leading to performance degradation. If used separately, other O
Even when switching to S, the information for the own OS remains, so there is no disturbance.
The performance improvement effect is significant.

〔Effect of the invention〕

As explained above, according to the present invention, by dividing the address translation buffer into a plurality of sections and giving priority to the allocation, when running a plurality of program modules or a plurality of OSs, the program module or the OS Even if the addresses are switched, the adverse effects can be expected to be minimized, and flexible address translation buffer control becomes possible.

[Brief explanation of the drawing]

1 is a block diagram of an embodiment of the present invention, FIG. 2 is a detailed diagram of the t-action allocation table of FIG. 1, FIG. 3 is a detailed diagram of the section index circuit of FIG. 1, and FIG. 4 is a detailed diagram of the section index circuit of FIG. FIG. 1 is a detailed diagram of the key comparison circuit, FIGS. 5 and 6 are diagrams showing an example of section allocation of the address translation buffer, and FIG. 7 is a diagram illustrating the present invention in detail. 1...Logical address register, 2...ID register, 3...Address translation buffer. 30... Address conversion data register, 4... Update circuit, 5... Section allocation table, 6... Section number holding register, 7... Section index circuit, 8... Key comparison circuit, 9 ···selector,
10...Real address register. Figure 3 Figure 1 Figure 2 (CL) (b) Figure 5 Figure 6

Claims (1)

[Claims] (1) High-speed memory that uses a virtual memory method and stores address translation information obtained from previous address translation processing (
In an electronic computer equipped with an address translation buffer (hereinafter referred to as an address translation buffer), when the address translation buffer is divided into multiple areas and multiple tasks (program modules) or OS (operating system) are run, the address translation An address translation control method characterized in that at least one area in a buffer is preferentially allocated to store address translation information for a specific task or a specific OS.