JPS6325700B2 - - Google Patents
Info
- Publication number
- JPS6325700B2 JPS6325700B2 JP56101088A JP10108881A JPS6325700B2 JP S6325700 B2 JPS6325700 B2 JP S6325700B2 JP 56101088 A JP56101088 A JP 56101088A JP 10108881 A JP10108881 A JP 10108881A JP S6325700 B2 JPS6325700 B2 JP S6325700B2
- Authority
- JP
- Japan
- Prior art keywords
- diffusion
- film
- glass film
- silicon
- impurities
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P32/00—Diffusion of dopants within, into or out of wafers, substrates or parts of devices
- H10P32/10—Diffusion of dopants within, into or out of semiconductor bodies or layers
- H10P32/14—Diffusion of dopants within, into or out of semiconductor bodies or layers within a single semiconductor body or layer in a solid phase; between different semiconductor bodies or layers, both in a solid phase
Landscapes
- Formation Of Insulating Films (AREA)
Description
【発明の詳細な説明】
本発明は半導体装置の製造方法に関し、特に酸
化物拡散マスクを突き抜ける不所望の拡散を伴わ
ない拡散方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a diffusion method that does not involve undesired diffusion through an oxide diffusion mask.
半導体装置の製造において、拡散すべき不純物
を含有させたガラス被膜を酸化物拡散マスク上に
被覆させて選択拡散するプロセスが多用されてい
る。第1図を参照すると、1はシリコン基板、2
はシリコン酸化膜の拡散マスク、3は不純物を含
有するガラス被膜であり、このガラス被膜3は、
気相成長法、回転塗布法等により形成され得るも
のであり、不純物としても燐、硼素、砒素、アン
チモン等広く適用でき、特にアンチモンや砒素の
拡散に便利な方法である。 In the manufacture of semiconductor devices, a process of selectively diffusing impurities by coating an oxide diffusion mask with a glass film containing impurities to be diffused is often used. Referring to FIG. 1, 1 is a silicon substrate, 2
is a diffusion mask of silicon oxide film, 3 is a glass film containing impurities, and this glass film 3 is
It can be formed by a vapor phase growth method, a spin coating method, etc., and can be applied to a wide range of impurities such as phosphorus, boron, arsenic, and antimony, and is particularly convenient for diffusing antimony and arsenic.
この不純物を含有させたガラス被膜からの拡散
におて、一般にロゼツトと呼ばれる結晶化された
領域が現われ、このロゼツトが拡散領域外の拡散
マスク2において生ずる場合、突き抜け現象を起
し、目的とする拡散層4以外に不所望の拡散領域
5が形成されることが判明した。 During the diffusion from the glass film containing impurities, a crystallized region generally called a rosette appears, and when this rosette occurs in the diffusion mask 2 outside the diffusion region, a penetration phenomenon occurs and the target It has been found that an undesired diffusion region 5 is formed in addition to the diffusion layer 4.
一方、このロゼツトが拡散領域内に生じたとき
はガラス3を除去する際エツチレートが極めて遅
いため残査として残る。特にかかる拡散方法を埋
没拡散に適用した場合、このロゼツトがアイソレ
ーシヨン不良や、エピタキシヤル層欠陥の原因と
なつている。 On the other hand, when this rosette occurs in the diffusion region, it remains as a residue because the etching rate is extremely slow when the glass 3 is removed. Particularly when such a diffusion method is applied to buried diffusion, this rosette causes isolation failure and epitaxial layer defects.
ところで、ガラス膜3を用いた拡散では、拡散
窓の周辺にてガラス膜3が比較的厚く付着する結
果、当該部分での不純物量が他の平坦部に比し多
く、従つて拡散の結果は第1図に示した拡散形状
となることも知られている。これはガラス膜厚が
拡散領域での比抵抗に依存する膜厚で使用してい
るためであり、実用上避け得ない。 By the way, in diffusion using the glass film 3, as a result of the glass film 3 being relatively thickly attached around the diffusion window, the amount of impurities in this area is larger than in other flat areas, and therefore the diffusion result is It is also known that the diffusion shape shown in FIG. 1 is obtained. This is because the glass film thickness used depends on the specific resistance in the diffusion region, and cannot be avoided in practice.
従つて、拡散窓がある程度大きい場合に、第1
図に示した好ましくない拡散が生ずることとな
り、拡散窓が小さく、ガラス膜厚がほぼ一定とみ
なせるときは、均一深さの拡散が実現できる。 Therefore, if the diffusion window is large to some extent, the first
The undesirable diffusion shown in the figure will occur, and if the diffusion window is small and the glass film thickness can be considered to be approximately constant, diffusion with a uniform depth can be achieved.
本発明は、以上の問題点に鑑み、第1にロゼツ
トによる不所望の拡散を防止した拡散方法を提供
せんとするものであり、更に本発明は第2に拡散
深さを均一になし得る拡散方法を提供せんとする
ものである。 In view of the above problems, the present invention aims, firstly, to provide a diffusion method that prevents undesired diffusion due to rosettes, and secondly, to provide a diffusion method that can make the diffusion depth uniform. The purpose is to provide a method.
このため本発明では、半導体基板表面の所望拡
散領域上に、上部を第1の保護膜で覆われ、かつ
内部に不純物を含有するガラス膜を設け、該ガラ
ス膜で覆われない半導体基板表面上にのみ不純物
を含有しない第2の保護膜を設け、前記第1の保
護膜を除去してから拡散を行なう工程が含まれる
ことを特徴とする半導体装置の製造方法である。 Therefore, in the present invention, a glass film whose upper part is covered with the first protective film and which contains impurities inside is provided on the desired diffusion region on the surface of the semiconductor substrate, and the surface of the semiconductor substrate which is not covered with the glass film is This method of manufacturing a semiconductor device includes the step of providing a second protective film containing no impurities only in the first protective film, and performing diffusion after removing the first protective film.
以下本発明を図面に示した実施例に従がつて詳
述する。 The present invention will be described in detail below with reference to embodiments shown in the drawings.
第2図乃至第5図は第1の実施例を示す図面で
あり、第2図に示す通り、比抵抗が10〜20Ω・cm
のP型シリコン基板1の表面にアンチモンガラス
膜6を回転塗布法にて形成する。アニール処理に
より約2000Åのアンチモンを含む硅酸ガラス膜6
を得る。 Figures 2 to 5 are drawings showing the first embodiment, and as shown in Figure 2, the specific resistance is 10 to 20 Ωcm.
An antimony glass film 6 is formed on the surface of a P-type silicon substrate 1 by spin coating. Silicate glass film 6 containing approximately 2000 Å of antimony through annealing treatment
get.
続いて表面に厚さ1000Åのシリコン窒化膜7を
被着し、フオト・プロセス後、シリコン窒化膜を
プラズマエツチングし拡散領域にのみ残し、更に
シリコン窒化膜7をマスクとしてガラス膜6をプ
ラズマエツチングする(第3図参照)。 Next, a silicon nitride film 7 with a thickness of 1000 Å is deposited on the surface, and after a photo process, the silicon nitride film is plasma etched to leave it only in the diffusion region, and the glass film 6 is further plasma etched using the silicon nitride film 7 as a mask. (See Figure 3).
第4図の工程にて熱酸化を行ない、シリコンの
露出面に900℃45分水温100℃或いは1150℃45分乾
燥酸素で1500Å酸化膜8を生成する。 In the process shown in FIG. 4, thermal oxidation is carried out to form an oxide film 8 of 1500 Å on the exposed surface of the silicon using water at 900° C. for 45 minutes and water at 100° C. or dry oxygen at 1150° C. for 45 minutes.
第5図の工程にて窒化膜7を除去すべく熱燐酸
にて除去する。このとき、酸化膜8は約500Åエ
ツチングされる。この状態で1250℃で75分の拡散
を行なう。拡散雰囲気としては酸素分圧を20%と
する。この結果、アンチモン拡散層9は均一深さ
で、その表面抵抗は20Ω/□となる。 In the step shown in FIG. 5, the nitride film 7 is removed using hot phosphoric acid. At this time, the oxide film 8 is etched by about 500 Å. In this state, diffusion is performed at 1250°C for 75 minutes. The diffusion atmosphere has an oxygen partial pressure of 20%. As a result, the antimony diffusion layer 9 has a uniform depth and a surface resistance of 20Ω/□.
最後にガラス膜6のみ除去すればよい。この後
の熱処理は不要で、ガラス膜6を付着させた状態
のみで、拡散を終了できる。この拡散時において
酸化膜8は1000Å以上あれば実用上十分のマスク
効果があるから、酸化膜8は実質上、1000Å以上
であればよい。 Finally, only the glass film 6 needs to be removed. There is no need for subsequent heat treatment, and the diffusion can be completed only with the glass film 6 attached. At the time of this diffusion, if the oxide film 8 has a thickness of 1000 Å or more, it has a practically sufficient masking effect, so the oxide film 8 may substantially have a thickness of 1000 Å or more.
なお、拡散中の酸素分圧は拡散層9の表面濃度
を高める上で重要な要因であつて、実験では酸素
分圧が0%の場合に得られる表面抵抗が40Ω/□
であつても酸素分圧を40%以上とすれば、同一条
件の拡散にて表面抵抗を16Ω/□にまで低下でき
るし、20%の酸素分圧では20Ω/□に低下させる
ことができる。この意味で、拡散中は第5図に示
した如く、ガラス膜6上に酸素のバリアがない様
にしておくことが表面濃度の低減に有効である。
この実施例に示した拡散方法による場合には、拡
散領域外のロゼツトは皆無にできる。 Note that the oxygen partial pressure during diffusion is an important factor in increasing the surface concentration of the diffusion layer 9, and in experiments, the surface resistance obtained when the oxygen partial pressure is 0% is 40Ω/□.
Even if the oxygen partial pressure is 40% or more, the surface resistance can be reduced to 16Ω/□ under the same diffusion conditions, and at 20% oxygen partial pressure, it can be reduced to 20Ω/□. In this sense, it is effective to reduce the surface concentration by making sure that there is no oxygen barrier on the glass film 6, as shown in FIG. 5, during the diffusion.
In the case of the diffusion method shown in this embodiment, rosettes outside the diffusion region can be completely eliminated.
上記の実施例においては酸化膜8はシリコン基
板の熱酸化により形成したが、これはガラス膜6
からの外方拡散による不所望の拡散を阻止するも
のであるが、形成方法としては、上述の熱酸化に
限定されない。即ち、ガラス膜6のみのパターニ
ング後、これに用いたレジストをそのまま用いて
不純物を含まないシリコン酸化膜を付着させ、リ
フト・オフすることにより、ガラス膜6で覆われ
ないシリコンの露出面を被着する。この場合、ガ
ラス膜6上に不純物を含まないシリコン酸化膜を
重ねると、熱膨脹係数の相違により、拡散処理中
クラツクが生ずる難点がある。シリコンの露出面
を被覆する材料はシリコン酸化膜が最適である
が、これに限定されることはなく、シリコンオキ
シナイトライド・シリコン窒化膜等を用いること
ができる。 In the above embodiment, the oxide film 8 was formed by thermal oxidation of the silicon substrate;
However, the formation method is not limited to the above-mentioned thermal oxidation. That is, after patterning only the glass film 6, a silicon oxide film containing no impurities is deposited using the same resist used for this pattern and lifted off, thereby covering the exposed surface of the silicon that is not covered with the glass film 6. wear it. In this case, if a silicon oxide film containing no impurities is superimposed on the glass film 6, there is a problem that cracks will occur during the diffusion process due to the difference in coefficient of thermal expansion. The most suitable material for covering the exposed surface of silicon is a silicon oxide film, but the material is not limited to this, and silicon oxynitride, silicon nitride, etc. can also be used.
第6図乃至第7図に示した実施例は拡散領域内
でのロゼツトをも防止できる半導体装置の製法を
示したもので、第6図の如くP型シリコン基板1
の表面に多結晶シリコン10を約1000Åの厚さに
成長させる。これは、単結晶であつてもよい。こ
の場合、表面は清浄化でき、ロゼツトの核となる
不純物はない。 The embodiment shown in FIGS. 6 and 7 shows a method for manufacturing a semiconductor device that can also prevent rosettes in the diffusion region, and as shown in FIG.
Polycrystalline silicon 10 is grown on the surface to a thickness of about 1000 Å. This may be a single crystal. In this case, the surface can be cleaned and free of impurities that form the core of the rosette.
この後、不純物を含むガラス膜11を形成し、
続いて耐酸化性膜7を形成し、両者を所望パター
ンにエツチング処理する。 After that, a glass film 11 containing impurities is formed,
Subsequently, an oxidation-resistant film 7 is formed, and both are etched into a desired pattern.
ここで熱酸化を施し露出している多結晶シリコ
ン10をシリコン酸化膜8へ変換する。 Here, thermal oxidation is performed to convert exposed polycrystalline silicon 10 into silicon oxide film 8.
この後、耐酸化性膜7は除去し、所望領域へ多
結晶シリコン10を通して不純物を拡散し、最後
にガラス膜11を全面エツチングで除去し現われ
た多結晶シリコン10は酸化により除去すればよ
い。 Thereafter, the oxidation-resistant film 7 is removed, impurities are diffused into a desired region through the polycrystalline silicon 10, and finally the entire surface of the glass film 11 is removed by etching, and the polycrystalline silicon 10 that appears is removed by oxidation.
斯様にしてして拡散領域内でのロゼツトも防止
できる。 In this way rosettes within the diffusion region can also be prevented.
第1図は従来の拡散方法により得られたシリコ
ン基板の断面図、第2図乃至第5図は本発明の第
1の実施例になる半導体製造過程を示すシリコン
基板の各々の断面図、第6図および第7図は本発
明の第2の実施例になる半導体製造過程を示すシ
リコン基板の断面図である。
図中、1はP型シリコン基板、6と11は不純
物含有ガラス膜、7は耐酸化膜、8はシリコン酸
化膜、9は拡散領域、10は多結晶シリコンを示
す。
FIG. 1 is a cross-sectional view of a silicon substrate obtained by a conventional diffusion method, and FIGS. 2 to 5 are cross-sectional views of a silicon substrate showing a semiconductor manufacturing process according to a first embodiment of the present invention. 6 and 7 are cross-sectional views of a silicon substrate showing a semiconductor manufacturing process according to a second embodiment of the present invention. In the figure, 1 is a P-type silicon substrate, 6 and 11 are impurity-containing glass films, 7 is an oxidation-resistant film, 8 is a silicon oxide film, 9 is a diffusion region, and 10 is polycrystalline silicon.
Claims (1)
第1の保護膜で覆われ、かつ内部に不純物を含有
するガラス膜を設け、該ガラス膜で覆われない半
導体基板表面上にのみ不純物を含有しない第2の
保護膜を設け、前記第1の保護膜を除去してから
拡散を行なう工程が含まれることを特徴とする半
導体装置の製造方法。1. A glass film whose upper part is covered with a first protective film and which contains an impurity is provided on the desired diffusion region on the surface of the semiconductor substrate, and the impurity is contained only on the surface of the semiconductor substrate that is not covered with the glass film. 1. A method of manufacturing a semiconductor device, comprising the steps of: providing a second protective film that does not contain a carbonaceous material; and performing diffusion after removing the first protective film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56101088A JPS583225A (en) | 1981-06-29 | 1981-06-29 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56101088A JPS583225A (en) | 1981-06-29 | 1981-06-29 | Manufacture of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS583225A JPS583225A (en) | 1983-01-10 |
| JPS6325700B2 true JPS6325700B2 (en) | 1988-05-26 |
Family
ID=14291335
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56101088A Granted JPS583225A (en) | 1981-06-29 | 1981-06-29 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS583225A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02177535A (en) * | 1988-12-28 | 1990-07-10 | Matsushita Electron Corp | Manufacture of semiconductor device |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5512709A (en) * | 1978-07-12 | 1980-01-29 | Toshiba Corp | Manufactiring method of semiconductor device |
-
1981
- 1981-06-29 JP JP56101088A patent/JPS583225A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS583225A (en) | 1983-01-10 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CA1041227A (en) | Method for forming dielectric isolation combining dielectric deposition and thermal oxidation | |
| US5895252A (en) | Field oxidation by implanted oxygen (FIMOX) | |
| JPH11204633A (en) | Method of forming trench isolation | |
| US3600241A (en) | Method of fabricating semiconductor devices by diffusion | |
| US4039359A (en) | Method of manufacturing a flattened semiconductor device | |
| JPH0748491B2 (en) | Method for manufacturing integrated circuit semiconductor device | |
| US4465705A (en) | Method of making semiconductor devices | |
| US4050967A (en) | Method of selective aluminum diffusion | |
| JPS5544713A (en) | Semiconductor device | |
| JPH0473296B2 (en) | ||
| JPS5812732B2 (en) | Manufacturing method for semiconductor devices | |
| JPH049371B2 (en) | ||
| JPS6136381B2 (en) | ||
| JPH0122731B2 (en) | ||
| JPS63228732A (en) | Manufacture of semiconductor device | |
| JPH0258778B2 (en) | ||
| JPH079930B2 (en) | Method for manufacturing semiconductor device | |
| KR930008845B1 (en) | Device isolation method of semiconductor device | |
| JPH0117256B2 (en) | ||
| JPS5947466B2 (en) | Manufacturing method of semiconductor device | |
| JP3282265B2 (en) | Method for manufacturing semiconductor device | |
| JPH0420261B2 (en) | ||
| JPH0258848A (en) | Manufacture of semiconductor device | |
| JPS5867046A (en) | Manufacture of semiconductor device | |
| JPS5596652A (en) | Method of fabricating semiconductor device |