JPH0420261B2 - - Google Patents

Description

[Detailed Description of the Invention] (a) Technical Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, in particular, to simultaneously form a U-shaped groove in an inter-element isolation region and a collector isolation region of a semiconductor integrated circuit (IC). Regarding new manufacturing methods.

(b) Conventional technology and problems Previously, silicon nitride (Si ₃ N ₄ ) film was used.
IOP (Isolation with Oxide and Poly silicon)
A method of forming an isolation region between elements is known, in which the isolation region is etched to form a U-shaped groove, and silicon dioxide (SiO ₂ ) is deposited on the inner surface of the groove.
This is a method of forming a film and burying the inside of it with polycrystalline silicon.

However, recently the collector isolation region has also been formed into a U-shaped groove, and the inside of the groove has been filled with SiO _{2 .}
A method of embedding a film and a polycrystalline silicon film is used. Figure 1 shows a cross-sectional view of the process, and 1 is P
type silicon substrate, 2 is an n ⁺ type silicon crystal layer (this is the buried layer of the semiconductor element), 3 is an n type silicon crystal layer (this will be the formation region of the base and emitter), and such a silicon substrate On the other hand, the collector isolation region 4 has a depth that reaches directly above the n ⁺ type silicon layer 2 or the middle of the layer, and the element isolation region 5 has a depth that reaches the p-type silicon substrate 1. The reason why the collector isolation region is formed by dielectric isolation in this way is that a walled base 6 can be formed as shown in the figure, which reduces the junction area of the collector base, which has the advantage of reducing floating capacitance. Moreover, this collector isolation region does not necessarily have to be of the IOP type in which polycrystalline silicon is buried, but may be of the isoplanar type in which only a SiO ₂ film is formed.

However, as mentioned above, since the collector isolation region 4 and the element isolation region 5 have different depths, grooves are formed separately, and therefore two patterning and two etching steps are required. Then,
That only makes the process more complicated.

(c) Object of the Invention The present invention proposes a manufacturing method aimed at shortening such a forming process.

(d) Structure of the Invention According to the present invention, the above object is to grow a semiconductor layer of an opposite conductivity type on a semiconductor substrate of one conductivity type, to remove the etching on the upper surface thereof using the same etching agent as the semiconductor layer, and to have an etching ratio higher than that of the semiconductor layer. A process of depositing a small insulating film and then depositing a protective film on top of it, then selectively removing the protective film and insulating film on the element isolation region, and then selectively removing the protective film on the collector isolation region. Next, the protective film is used as a mask on the collector isolation region, and the protective film and insulating film are used as a mask on the element isolation region.
Etching the insulating film and semiconductor layer in the collector isolation region and the semiconductor layer in the element isolation region simultaneously by reactive-on etching to form U-shaped grooves with different depths in the collector isolation region and the element isolation region. This is achieved by a method for manufacturing a semiconductor layer, which is characterized in that it includes a step of removing the protective film over the entire surface.

(e) Embodiment of the invention Hereinafter, an embodiment will be described in detail with reference to the drawings. 2 to 5 show cross-sectional views in the order of steps according to the present invention. First, as shown in FIG.
An n ⁺ type silicon layer 12 with a thickness of 1.5 μm and an n type silicon layer 13 with a thickness of 1.5 μm are epitaxially grown on a silicon substrate 11, and a layer with a thickness of 0.15 μm is grown on the upper surface thereof.
_An insulating film consisting of a _{SiO 2} film 14 of It adheres to the skin. Here, the SiO ₂ film 14 is a buffer layer interposed between the Si ₃ N ₄ film and the silicon substrate surface so as not to damage the silicon substrate surface.

Next, as shown in FIG. 3, a resist film mask (not shown) is formed on the element formation region 18 including the collector isolation region 17, and reactive-on-etching is performed using trifluoromethane (CHF ₃ ) gas. Then, the PSG film 16, Si ₃ N ₄ film 15 and SiO ₂ film 14 on the inter-element isolation region 19 are removed by etching, and then another resist film mask (not shown) is formed again to remove the collector isolation region. 17
is exposed, other regions are covered with a mask, and only the PSG film 16 on the collector isolation region 17 is etched away by wet etching using hydrofluoric acid or reactive on etching using CHF ₃ gas.

Next, as shown in Figure 4, the entire surface was etched by reactive on-etching using a mixed gas of carbon tetrachloride (Ccl ₄ ) and boron trichloride (BCl ₃ ) at a reduced pressure of 0.1 ^Torr and an output of 650 ^W. When etching is performed at the same time, as shown in the figure, the U-shaped groove in the collector isolation region 17 reaches the n ⁺ type silicon layer 12, and at the same time, the U-shaped groove in the element isolation region 19 penetrates through the n ⁺ type silicon layer to form a p-type etched layer. It can even reach the silicon substrate 11. That is, since the etching ratio of the mask material consisting of the Si ₃ N ₄ film 15 and the SiO ₂ film 14 to silicon is 1:4 to 5, the film thickness is
Before the mask material of 0.15+0.35=0.5 μm is etched away on the collector isolation region 17, the silicon layer of 0.5 μm×(4-5)=2-2.5 μm is etched in the element isolation region 19. When the etching progresses further and the 1.5 μm thick n-type silicon layer in the collector isolation region is etched away, the inter-element isolation region 19 is also etched to a thickness of 1.5 μm. μm)+1.5μm=3.5~4μ
m U-shaped grooves are formed.

For this purpose, the U-shaped groove in the collector isolation region ^is
When reaching the type silicon layer, the U-shaped groove of the element isolation region reaches the P-type silicon substrate 11. At this time, since there is a mask with a film thickness of 1.5 μm in the element forming region 18 covered with the mask material consisting of the PSG film 16, Si ₃ N ₄ film 15, and SiO ₂ film, silicon is coated with a thickness of 6 to 7.5 μm. It will not be exposed unless it is etched. Therefore, the element formation region is sufficiently masked. In simultaneous opening of windows in both areas, since both windows have small steps, the opening process becomes easy and can be formed with high precision.

Next, as shown in FIG. 5, the PSG film 1 on the top surface is
After etching 6 with hydrofluoric acid, the inside of the U-shaped groove of the element isolation region 17 and the collector isolation region 19 is buried with a SiO ₂ film 20 and a polycrystalline silicon film 21 by the well-known IOP method. Moreover, instead of the cross-sectional structure shown in FIG. 5, only the SiO ₂ film may be buried by CVD.

In the above embodiment, the insulating film is a Si ₃ N ₄ film with an SiO ₂ film interposed therebetween, and the protective film is a PSG film, but other insulating films or protective films may be used. In this case, it is desirable that the insulating film and the protective film be etched with the same etching agent, thereby simplifying the etching process.

(f) Effects of the Invention As can be seen from the above explanation, according to the present invention, U-shaped grooves of different depths are formed at the same time by etching, which shortens the manufacturing process and has a positive effect on improving yield and quality. It gives

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view of the process of forming an element isolation region and a collector isolation region, and FIGS. 2 to 5 are sequential cross-sectional views of the manufacturing process according to the present invention. In the figure,
1 and 11 are P-type silicon substrates, 2 and 12 are n ⁺ type silicon layers, 3 and 13 are n-type silicon layers, 4 and 1
7 is a collector isolation region, 5 and 19 are element isolation regions, 14 is a SiO ₂ film, 15 is a Si ₃ N ₄ film, 16 is a PSG
A film 18 indicates an element formation region.

Claims (1)

[Claims] 1. A semiconductor layer of an opposite conductivity type is grown on a semiconductor substrate of one conductivity type, and an insulating film that can be etched away using the same etching agent as the semiconductor layer and has a lower etching ratio than the semiconductor layer is deposited on the top surface of the semiconductor layer, and then an insulating film is deposited on top of the semiconductor layer. A step of depositing a protective film, then a step of selectively removing the protective film and an insulating film on the element isolation region, a step of selectively removing the protective film on the collector isolation region, and then a step of selectively removing the protective film on the collector isolation region. etching the insulating film and the semiconductor layer in the collector isolation region and the semiconductor layer in the element isolation region simultaneously by reactive-on etching, using the film as a mask and using the protective film and the insulating film as masks on the element isolation region; 1. A method for manufacturing a semiconductor layer, comprising the steps of forming U-shaped grooves with different depths in a collector isolation region and an element isolation region, and then removing a protective film entirely.