JPS6325954A - Semiconductor device and manufacture thereof - Google Patents
Semiconductor device and manufacture thereofInfo
- Publication number
- JPS6325954A JPS6325954A JP61169126A JP16912686A JPS6325954A JP S6325954 A JPS6325954 A JP S6325954A JP 61169126 A JP61169126 A JP 61169126A JP 16912686 A JP16912686 A JP 16912686A JP S6325954 A JPS6325954 A JP S6325954A
- Authority
- JP
- Japan
- Prior art keywords
- conductor layer
- film
- window
- conductor
- cover
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/01—Manufacture or treatment
- H10W72/012—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps
Landscapes
- Wire Bonding (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置及びその製造方法に関し、特に突起
電極を有する半導体装置及びその製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a semiconductor device having protruding electrodes and a method for manufacturing the same.
最近、半導体装置の高密度実装のためやごく最近のカー
ド用ICの薄型1ヒのために、従来のワイヤーボンディ
ングに代り、テープ自動ボンディング(TAB)の技術
が使用されてきている。このために、半導体ウェーハプ
ロセスでは、ICチップのボンディング領域に突起電極
(以降バンブと称す)を設ける方式が一般的となってい
る。Recently, tape automatic bonding (TAB) technology has been used in place of conventional wire bonding for high-density packaging of semiconductor devices and for the very recent thin ICs for cards. For this reason, in semiconductor wafer processes, it has become common to provide protruding electrodes (hereinafter referred to as bumps) in the bonding regions of IC chips.
第4図は従来の半導体装置の一例の断面図である。FIG. 4 is a sectional view of an example of a conventional semiconductor device.
この従来例は、シリコン基板1上に内部の半導体素子と
接続したAff電極3を設け、その上にA2電極3上に
開孔部を有する絶縁膜2を設け、開孔部と開孔部周辺の
絶縁膜2とを覆うように金属層4″、5″、6″及びパ
ン18″を積層するように設け、金属層4″、5″、6
′″及びパン18″の側面を覆うようにポリイミド膜9
″を設けた構造をしている。In this conventional example, an Aff electrode 3 connected to an internal semiconductor element is provided on a silicon substrate 1, an insulating film 2 having an opening is provided on the A2 electrode 3, and the opening and the surrounding area of the opening are provided. The metal layers 4'', 5'', 6'' and the pan 18'' are stacked so as to cover the insulating film 2 of the metal layers 4'', 5'', 6''.
'' and the sides of the pan 18''.
It has a structure with ``.
第5図(a)〜(g)は従来の半導体装置の製造方法の
一例を説明するための半導体チップの断面図である。FIGS. 5(a) to 5(g) are cross-sectional views of a semiconductor chip for explaining an example of a conventional method for manufacturing a semiconductor device.
この例はまず、第5図(a)に示すように、シリコン基
板1上のボンディング領域の絶縁膜2をホトエツチング
法により開孔し、ボンディング領域のAf電極3表面を
露出させる。In this example, first, as shown in FIG. 5(a), a hole is formed in the insulating film 2 in the bonding region on the silicon substrate 1 by photoetching to expose the surface of the Af electrode 3 in the bonding region.
次に、第5図(b)に示すように、Ae電極3との接着
用の金属N4″、中間にあって障壁用となる金属層5″
及びめっき法で形成されるバンブと直接接する金属層6
″例えば金を全面に連続的に被着する。Next, as shown in FIG. 5(b), there is a metal layer N4'' for adhesion to the Ae electrode 3, and a metal layer 5'' located in the middle that serves as a barrier.
and a metal layer 6 in direct contact with the bump formed by plating.
``For example, gold is continuously deposited on the entire surface.
次に、第5図(C)に示すように、ホトレジスト7″を
所定のパターンでバンブを形成しようとしている開孔部
を除いて形成する。Next, as shown in FIG. 5C, photoresist 7'' is formed in a predetermined pattern except for the openings where bumps are to be formed.
この後、第5図(d)に示すように、ホトレジスト7″
を保護膜として金あるいは銅のめっきを施し、所望の高
さの金属のパン18″を形成する。After this, as shown in FIG. 5(d), the photoresist 7''
is plated with gold or copper as a protective film to form a metal pan 18'' of a desired height.
次に、第5図(e)に示すように、不要となったホトレ
ジスト7″を除去した後、金属層6″、金属層5″及び
第1の金属層4″を順次エツチングし、バンブを形成す
る。Next, as shown in FIG. 5(e), after removing the unnecessary photoresist 7'', the metal layer 6'', the metal layer 5'' and the first metal layer 4'' are sequentially etched to remove the bumps. Form.
この後、通常は素子表面の保護とボンディング時の機械
的衝撃やストレスを吸収する目的で第5図(f)に示す
ように、ポリイミド膜9″をバンブを覆うように半導体
チップの表面に形成する。After this, a polyimide film 9'' is usually formed on the surface of the semiconductor chip to cover the bumps, as shown in FIG. 5(f), for the purpose of protecting the element surface and absorbing mechanical shock and stress during bonding. do.
次に、第5図(g>に示すように、パン18″の上部を
開孔したホトレジスト10″を形成する。Next, as shown in FIG. 5(g>), a photoresist 10'' is formed with holes formed in the upper part of the pan 18''.
最後に、ホトレジスト10″をマスクとしてポリイミド
膜9″をエツチングした後ホトレジスト10″を除去す
れば、第4図に示すような、従来の半導体装置の一例が
できる。Finally, by etching the polyimide film 9'' using the photoresist 10'' as a mask and removing the photoresist 10'', an example of a conventional semiconductor device as shown in FIG. 4 is obtained.
上述した従来の半導体装置及びその製造方法では、第1
の導体層であるAI!電極上に開孔部を有する絶縁膜表
面に直接接着用の第2の導体層、障壁用の第3の導体層
を含む複数の導体層を積層するので、その導体層に使う
金属の種類がパターニングするためのエツチング等の条
件によって非常に限られるという欠点がある。例えばp
t3第3の導体層に使用する場合には、湿式エツチング
によってパターニングするには熱王水を使うので適当な
保護マスクが無く、イオンミリングあるいは最近の反応
性イオンエツチング等の一般的な乾式エツチングではシ
リコン基板上に半導体素子を形成する過程で生じる種々
の段差部にエツチングされた白金が再付着して短絡不良
を起すので、ptを含むTi−Pt−Au三層によって
構成される複数の導体層を使うことができないという欠
点がある。In the conventional semiconductor device and its manufacturing method described above, the first
AI! which is the conductor layer of Since multiple conductor layers including a second conductor layer for direct adhesion and a third conductor layer for barrier are laminated on the surface of an insulating film having openings on the electrode, the type of metal used for the conductor layer is The drawback is that it is very limited depending on conditions such as etching for patterning. For example p
t3 When used for the third conductor layer, patterning by wet etching requires hot aqua regia, so there is no appropriate protective mask, and general dry etching such as ion milling or recent reactive ion etching Etched platinum re-adheres to various step portions that occur during the process of forming semiconductor devices on a silicon substrate, causing short-circuit defects. The disadvantage is that it cannot be used.
又、この従来例のようにバンブの側面をポリイミド膜で
覆った構造では、ホトリソグラフィー工程中の百合せず
れや、ポリイミド膜のエツチング時のアンダーカット等
によりポリイミド膜をバンブの側面に接して安定に形成
することが非常に困難であり、これらに起因するボンデ
ィング不良等によって製造歩留りが低下するという欠点
もある。In addition, in a structure in which the side surface of the bump is covered with a polyimide film as in this conventional example, the polyimide film is not stable when it is in contact with the side surface of the bump due to misalignment during the photolithography process or undercut during etching of the polyimide film. It is very difficult to form the same, and there is also the drawback that manufacturing yield is reduced due to bonding defects caused by these.
本発明の目的は、半導体基板上の第1の導体層とバンブ
との間をつなぐ複数の導体層として種々の金属が使えて
しかもポリイミド膜がバンブの側面に安定に接して形成
でき製造歩留りの高い半導体装置及びその製造方法を提
供することにある。An object of the present invention is to use various metals as the plurality of conductor layers connecting the first conductor layer on the semiconductor substrate and the bumps, and to form a polyimide film in stable contact with the side surfaces of the bumps, thereby reducing the manufacturing yield. An object of the present invention is to provide a high quality semiconductor device and a method for manufacturing the same.
本発明の半導体装置は、半導体素子が形成さている半導
体基板上に前記半導体素子と接続した第1の導体層を設
け、該第1の導体層を覆いかつ前記第1の導体層上の所
定の位置にコンタクト用の窓を有する絶縁性の第1の膜
と樹脂性の第2の膜との積層膜を設け、該積層膜の前記
窓と前記樹脂性の第2の膜の前記窓周辺とを覆うように
所定のパターンで前記第1の導体層との接着用の第2の
導体層と障壁用の第3の導体層とを少くとも含む複数の
導体層を設け、該複数の導体層上に突起電極を設けて成
る。In the semiconductor device of the present invention, a first conductor layer connected to the semiconductor element is provided on a semiconductor substrate on which a semiconductor element is formed, and a predetermined conductor layer is provided on the first conductor layer and covers the first conductor layer. A laminated film of an insulating first film and a resinous second film having a contact window at a position is provided, and the window of the laminated film and the periphery of the window of the resinous second film are arranged. a plurality of conductor layers including at least a second conductor layer for adhesion to the first conductor layer and a third conductor layer for a barrier are provided in a predetermined pattern so as to cover the plurality of conductor layers; A protruding electrode is provided on the top.
本発明の半導体装置の製造方法は、半導体素子が形成さ
れた半導体基板上に前記半導体素子と接続した第1の導
体層を形成する工程と、前記第1の導体層を覆いかつ前
記第1の導体層上の所定の位置にコンタクト用の窓を有
する絶縁性の第1の膜と樹脂性の第2の膜との積層膜を
形成する工程と、前記積層膜の前記窓と前記樹脂性の第
2の膜の前記窓周辺とを覆うように前記第1の導体層と
の接着用の第2の導体層と障壁用の第3の導体層とを少
くとも含む複数の導体層とを順次積層する工程と、前記
複数の導体層上に前記窓を囲むような開孔部を有するホ
トレジスト膜を形成する工程と、該ホトレジスト膜の開
孔部を覆うように突起電極を形成する工程と、前記ホト
レジスト膜を除去した後に前記突起電極をマスクとして
前記複数の導体層を除去する工程とを含んで構成される
。The method for manufacturing a semiconductor device of the present invention includes the steps of: forming a first conductor layer connected to the semiconductor element on a semiconductor substrate on which a semiconductor element is formed; forming a laminated film of an insulating first film and a resinous second film having contact windows at predetermined positions on the conductor layer; a plurality of conductor layers including at least a second conductor layer for adhesion to the first conductor layer and a third conductor layer for a barrier so as to cover the second film around the window; a step of laminating, a step of forming a photoresist film having an aperture surrounding the window on the plurality of conductor layers, a step of forming a protruding electrode so as to cover the aperture of the photoresist film; The method includes a step of removing the plurality of conductor layers using the protruding electrode as a mask after removing the photoresist film.
次に、本発明の実施例について図面を参照して説明する
。Next, embodiments of the present invention will be described with reference to the drawings.
第1図は本発明の半導体装置の第1の実施例の四面図で
ある。FIG. 1 is a four-sided view of a first embodiment of the semiconductor device of the present invention.
この第1の実施例は、半導体素子を形成したシリコン基
板1上に半導体素子と接続したAl電極3を設け、Ae
電極3の所定の位置に開孔部を有しかつAI!電極3と
シリコン基板1とを覆うように絶縁膜2を設け、絶縁膜
2の開孔部より狭いAl電極3のコンタクト用の窓を有
しかつ絶縁膜2を覆うようにポリイミド膜9を設け、コ
ンタクト用の窓及び窓周辺のポリイミド膜9を覆うよう
にAJ?電f!3との接着用の金属層4、障壁用の金属
層5及びバンブと直接接する金属層6の3層を積層した
複数の金属層を設け、金属層4,5及び6の上にバンブ
8を設けた構造をしている。In this first embodiment, an Al electrode 3 connected to the semiconductor element is provided on a silicon substrate 1 on which a semiconductor element is formed, and an Ae
The electrode 3 has an opening at a predetermined position, and AI! An insulating film 2 is provided to cover the electrode 3 and the silicon substrate 1, and a polyimide film 9 is provided to have a contact window for the Al electrode 3 that is narrower than the opening of the insulating film 2 and to cover the insulating film 2. , AJ? so as to cover the contact window and the polyimide film 9 around the window. Electric f! A plurality of metal layers are provided in which three layers are laminated: a metal layer 4 for adhesion with the bumps 3, a metal layer 5 for a barrier, and a metal layer 6 in direct contact with the bumps, and the bumps 8 are placed on top of the metal layers 4, 5, and 6. It has a set structure.
第2図は本発明の半導体装置の第2の実施例の断面図で
ある。FIG. 2 is a sectional view of a second embodiment of the semiconductor device of the present invention.
第2の実施例は、シリコン基板1上にA!!電極3と絶
縁膜2とを設けるところまでは上述の第1の実施例と同
じであるが、絶縁膜2より上が、絶縁膜2の開孔部を囲
むように大きく開孔したポリイミド膜9′を絶縁膜2上
に設け、絶縁膜2の開孔部をコンタクト用の窓としてそ
の窓と窓周辺の絶縁膜2及びポリイミド膜9′とを覆う
ように積層した金属層4′、5’及び6′を設け、金属
層4′、5′及び6′の上にパン18′を設けた構造に
なっている。In the second embodiment, A! ! The provision of the electrode 3 and the insulating film 2 is the same as in the first embodiment described above, but above the insulating film 2 there is a polyimide film 9 with large openings surrounding the opening of the insulating film 2. ' are provided on the insulating film 2, and metal layers 4' and 5' are laminated so as to cover the window, the insulating film 2 around the window, and the polyimide film 9', using the opening of the insulating film 2 as a contact window. and 6' are provided, and a pan 18' is provided on the metal layers 4', 5' and 6'.
第3図(a)〜(g>は本発明の半導体装置の製造方法
の一実施例を説明するための工程順に示した半導体チッ
プの断面図である。FIGS. 3A to 3G are cross-sectional views of a semiconductor chip shown in the order of steps for explaining an embodiment of the method for manufacturing a semiconductor device of the present invention.
この実施例は、先ず、第3図(a>に示すように、シリ
コン基板1上に形成されかつ半導体素子と接続したAI
!電極3上の所定の位置の絶縁膜2を通常のエツチング
法により開孔し、Al電極3の表面を露出する。In this embodiment, first, as shown in FIG. 3(a), an AI
! A hole is opened in the insulating film 2 at a predetermined position on the electrode 3 by a normal etching method, and the surface of the Al electrode 3 is exposed.
次に、第3図(b)に示すように、ポリイミド膜9を回
転塗布法により全面に形成し、適当な熱処理によってキ
ュアされた後、コンタクト用の窓に相当する開孔部をも
つようにホトレジストを通常のホトリソグラフィプロセ
スにより形成する。Next, as shown in FIG. 3(b), a polyimide film 9 is formed over the entire surface by a spin coating method, and after being cured by an appropriate heat treatment, a polyimide film 9 is formed to have an opening corresponding to a contact window. A photoresist is formed by a conventional photolithography process.
次に、第3図(C)に示すように、ホトレジスト膜をマ
スクとしてポリイミド膜9をエツチングした後、不要と
なったホトレジスト7を除去する。Next, as shown in FIG. 3C, the polyimide film 9 is etched using the photoresist film as a mask, and then the unnecessary photoresist 7 is removed.
次に、第3図(d)に示すように、A/電極との接着用
の金属層4、障壁用の金属層5及びバンブと直接接する
金属層6を全面に連続的に堆積する。この実施例では、
三層の金属層を使用する例をあげているが、勿論二層の
金属層でも良い。Next, as shown in FIG. 3(d), a metal layer 4 for adhesion to the A/electrode, a metal layer 5 for a barrier, and a metal layer 6 in direct contact with the bumps are successively deposited over the entire surface. In this example,
Although an example is given in which three metal layers are used, of course two metal layers may be used.
次に、第3図(e)に示すように、コンタクト用の窓を
囲むような開孔部を有するホトレジスト10を形成する
。Next, as shown in FIG. 3(e), a photoresist 10 having an opening surrounding the contact window is formed.
次に、第3図(f)に示すように、ホトレジスト10を
保護膜として金あるいは銅等のバンプ8をめっき法で形
成する。Next, as shown in FIG. 3(f), bumps 8 of gold, copper, or the like are formed by plating using the photoresist 10 as a protective film.
次に、第3図(g)に示すように、ホトレジスト10を
除去する。Next, as shown in FIG. 3(g), the photoresist 10 is removed.
最後に、露出した部分の金属層6.5及び4を順次除去
すれば、第1図に示すような本発明の半導体装置の第1
の実施例ができる。Finally, by sequentially removing the exposed portions of the metal layers 6.5 and 4, the first semiconductor device of the present invention as shown in FIG.
An example of this can be done.
以上説明したように本発明は、ポリイミド膜をバンプ下
の複数の金属層を積層した導体層の下に形成するので、
導体層のエツチングの時に、半導体チップの表面を保護
すると共に段差のある部分が均らされ、乾式エツチング
時の段差部への再付着の問題が無くなって乾式エツチン
グが使えるようになり、導体層としてTi−Pt−Au
の三層は勿論Cr−Cu−Au三層、T i −P d
−A u三層、Ti−Cu−Au三層各種の組合せよ
る導体層が幅広く使えるようになるという効果がある。As explained above, in the present invention, a polyimide film is formed under a conductor layer formed by laminating a plurality of metal layers under the bump.
When etching the conductor layer, it protects the surface of the semiconductor chip and evens out the uneven parts, eliminating the problem of re-adhering to the uneven parts during dry etching, making it possible to use dry etching. Ti-Pt-Au
Of course, the three layers are Cr-Cu-Au three layers, Ti-Pd
- There is an effect that conductor layers that can be combined with various combinations of three layers of Au and three layers of Ti-Cu-Au can be widely used.
又、バンプ側面の下の部分にポリイミド膜が接して設け
られているので、これがボンディング時の機械的及び熱
的衝撃やストレスを緩和し、ボンディング剥れ不良を防
止すると共に従来のようにポリイミド膜をバンプの側面
全体に接して形成するような場合に問題となっていた目
金せずれやアンダーカットによる製造歩留りの低下がほ
とんど起こらないという効果もある。In addition, since the polyimide film is provided in contact with the lower part of the side surface of the bump, this reduces mechanical and thermal shock and stress during bonding, prevents bonding peeling defects, and prevents the polyimide film from being used as in the conventional case. Another advantage is that there is almost no reduction in manufacturing yield due to misalignment or undercut, which was a problem when the bump was formed in contact with the entire side surface of the bump.
の第1及び第2の実施例の断面図、第3図(a)〜(g
)は本発明の半導体装置の製造方法の一実施例を説明す
るための工程順に示した半導体チップの断面図、第4図
は従来の半導体装置の一例の断面図、第5図(a)〜(
g)は従来の半導体装置の製造方法の一例を説明するた
めの半導体チップの断面図である。Cross-sectional views of the first and second embodiments, FIGS. 3(a) to (g)
) is a cross-sectional view of a semiconductor chip shown in the order of steps for explaining one embodiment of the method for manufacturing a semiconductor device of the present invention, FIG. 4 is a cross-sectional view of an example of a conventional semiconductor device, and FIGS. (
g) is a cross-sectional view of a semiconductor chip for explaining an example of a conventional method for manufacturing a semiconductor device.
1・・・シリコン基板、2・・・絶縁膜、3・・・AI
!電極、4.4’、4”、5.5’ 、5″、6.6”
、6“・・・金属層、7,7″・・・ホトレジスト、8
,8′、8″・・・バンプ、9.9’ 、9“・・・ポ
リイミド膜、10.10″・・・ホトレジスト。1... Silicon substrate, 2... Insulating film, 3... AI
! Electrode, 4.4', 4", 5.5', 5", 6.6"
, 6"...metal layer, 7,7"...photoresist, 8
, 8', 8''...bump, 9.9', 9''...polyimide film, 10.10''...photoresist.
Claims (2)
導体素子と接続した第1の導体層を設け、該第1の導体
層を覆いかつ前記第1の導体層上の所定の位置にコンタ
クト用の窓を有する絶縁性の第1の膜と樹脂性の第2の
膜との積層膜を設け、該積層膜の前記窓と前記樹脂性の
第2の膜の前記窓周辺とを覆うように所定のパターンで
前記第1の導体層との接着用の第2の導体層と障壁用の
第3の導体層とを少くとも含む複数の導体層を設け、該
複数の導体層上に突起電極を設けたことを特徴とする半
導体装置。(1) A first conductor layer connected to the semiconductor element is provided on a semiconductor substrate on which a semiconductor element is formed, and a contact layer is provided at a predetermined position on the first conductor layer and covers the first conductor layer. A laminated film of an insulating first film and a resinous second film having a window is provided, and the window of the laminated film and the area around the window of the resinous second film are covered. A plurality of conductor layers including at least a second conductor layer for adhesion to the first conductor layer and a third conductor layer for a barrier are provided in a predetermined pattern, and protruding electrodes are provided on the plurality of conductor layers. A semiconductor device characterized by being provided with.
体素子と接続した第1の導体層を形成する工程と、前記
第1の導体層を覆いかつ前記第1の導体層上の所定の位
置にコンタクト用の窓を有する絶縁性の第1の膜と樹脂
性の第2の膜との積層膜を形成する工程と、前記積層膜
の前記窓と前記樹脂性の第2の膜の前記窓周辺とを覆う
ように前記第1の導体層との接着用の第2の導体層と障
壁用の第3の導体層とを少くとも含む複数の導体層とを
順次積層する工程と、前記複数の導体層上に前記窓を囲
むような開孔部を有するホトレジスト膜を形成する工程
と、該ホトレジスト膜の開孔部を覆うように突起電極を
形成する工程と、前記ホトレジスト膜を除去した後に前
記突起電極をマスクとして前記複数の導体層を除去する
工程とを含むことを特徴とする半導体装置の製造方法。(2) forming a first conductor layer connected to the semiconductor element on the semiconductor substrate on which the semiconductor element is formed; and covering the first conductor layer and positioning the first conductor layer at a predetermined position on the first conductor layer; forming a laminated film of an insulating first film and a resinous second film having a contact window in the laminated film and the window of the resinous second film; a step of sequentially laminating a plurality of conductor layers including at least a second conductor layer for adhesion to the first conductor layer and a third conductor layer for a barrier so as to cover the periphery; forming a photoresist film having an opening surrounding the window on the conductor layer; forming a protruding electrode to cover the opening of the photoresist film; and after removing the photoresist film. A method of manufacturing a semiconductor device, comprising the step of removing the plurality of conductor layers using the protruding electrode as a mask.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61169126A JPH0732157B2 (en) | 1986-07-17 | 1986-07-17 | Semiconductor device and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61169126A JPH0732157B2 (en) | 1986-07-17 | 1986-07-17 | Semiconductor device and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6325954A true JPS6325954A (en) | 1988-02-03 |
| JPH0732157B2 JPH0732157B2 (en) | 1995-04-10 |
Family
ID=15880761
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61169126A Expired - Lifetime JPH0732157B2 (en) | 1986-07-17 | 1986-07-17 | Semiconductor device and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0732157B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01276647A (en) * | 1988-04-27 | 1989-11-07 | Casio Comput Co Ltd | Formation of electrode for semiconductor device and etching device therefor |
| JPH02125621A (en) * | 1988-11-04 | 1990-05-14 | Nec Corp | Bump electrode forming method for semiconductor device |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5850756A (en) * | 1981-09-19 | 1983-03-25 | Ricoh Elemex Corp | Bump formation method |
-
1986
- 1986-07-17 JP JP61169126A patent/JPH0732157B2/en not_active Expired - Lifetime
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5850756A (en) * | 1981-09-19 | 1983-03-25 | Ricoh Elemex Corp | Bump formation method |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01276647A (en) * | 1988-04-27 | 1989-11-07 | Casio Comput Co Ltd | Formation of electrode for semiconductor device and etching device therefor |
| JPH02125621A (en) * | 1988-11-04 | 1990-05-14 | Nec Corp | Bump electrode forming method for semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0732157B2 (en) | 1995-04-10 |
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