JPS63260077A - semiconductor equipment - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to the structure of a high-speed bipolar transistor.

[Prior art] Conventionally, in bipolar transistors, the active region is usually formed in an epitaxial growth layer, and speed increases are achieved by thinning the shrimp layer, making shallow junctions, and lowering junction capacitance. Recently, thin film transistors with a thickness of around 1 μm have finally been put into practical use.

[Problem that the invention seeks to solve]

However, in order to increase the speed of this conventional bipolar transistor, it is necessary to make the epitaxial growth layer thinner, and it is necessary to control the thickness of the epitaxial layer, resistivity, buried layer concentration, and autodoping. Manufacturing technology, such as control, is becoming increasingly difficult.

On the other hand, as a manufacturing technology that does not use an epitaxial layer,
A diffused collector method, a triple diffusion method, etc. have been developed in the past, but they are hardly used today because of the increased junction capacitance and the difficulty of manufacturing methods.

Furthermore, in this conventional structure, the thickness of the epitaxial layer is the same everywhere on the substrate, so if an element with different characteristics is to be obtained on one substrate, it is restricted by the thickness of the epitaxial layer. Furthermore, when forming isolation regions between elements, the isobrain method or dielectric isolation method (trench isolation method) is used to reduce the junction capacitance as much as possible, but the junction capacitance between the element and the substrate, that is, the vertical capacitance has the disadvantage that it cannot be easily reduced.

In view of the above circumstances, an object of the present invention is to provide a semiconductor device that is completely separated from a substrate in both vertical and horizontal directions and can be constructed without using an epitaxial layer. Means] According to the present invention, a semiconductor device includes a semiconductor substrate, an emitter and a base region provided in a crystal plane different from a crystal plane on the surface of the semiconductor substrate, and a complementary crystal plane of the crystal plane forming the emitter and base regions. and an element isolation region formed of a substrate oxide film formed at a connection portion between the two crystal planes and the substrate.

〔Example〕 Hereinafter, the present invention will be described in detail with reference to the drawings.

Since it is believed that the structure of the semiconductor device of the present invention can be best understood by clarifying its manufacturing method, it will be explained along with the manufacturing process.

FIGS. 1 to 7 show a bipolar
FIG. 3 is a manufacturing process diagram for clarifying the transistor structure. First, a silicon oxide film 12 is placed on an N-type silicon substrate 11 (0.5 to 2 Ω·l) whose surface crystal plane is <100>.
After growing, this silicon oxide film 12 is selectively etched to form an arbitrary pattern (see FIG. 1).

Next, using the silicon oxide film 12 as a mask, sulfur hexafluoride (SF) is applied at an angle of 45° to the surface of the silicon substrate 11.
6) and carbon tetrachloride CCCe4>, the silicon substrate 11 is anisotropically etched to a desired depth by reactive ion etching (RIE), and the silicon oxide film 12 used as a mask is removed ( (See Figure 2), at this time, the protruding silicon 13 with an angle of 45°
The crystal plane that can be seen from the top surface is <110>, and the crystal plane on the back surface that cannot be seen is <110>.Next, about 500 silicon oxide fi14 were deposited on the entire surface of the silicon substrate 11.
After forming a silicon nitride film 15 of approximately 1000 layers,
<11 of the protruding silicon 13 using the positive resist 16
Selective etching of the bottom of the crystal plane of <110> (see Figure 3).
0> is selectively oxidized to form an element isolation region 17, electrically insulating and isolating the protruding silicon 13 from the silicon substrate 11 (see FIG. 4), and then selecting a silicon nitride film 15. A base region 18 is formed by etching and thermal diffusion or ion implantation of boron, and a silicon oxide film 19 is formed on the surface (see FIG. 5). After removing a portion of the silicon nitride film 15 and the silicon oxide film 14 on the <110> plane that follow it, phosphorus is thermally diffused to form a highly concentrated collector region 20, and then a silicon oxide film 21 is formed on the surface. Then, the silicon oxide film 19 on the base region 18 is selectively etched and arsenic is thermally diffused or ion-implanted to form the emitter region 22 (see FIG. 6).
. Here, a highly concentrated collector region 20 and an emitter region 22
were formed separately, but it is okay to form them at the same time.
・Finally, after opening an electrode extraction window in each region and depositing an aluminum film, perform arbitrary patterning to form the electrodes 23 (see Figure 7). Aluminum was used directly, but the upper surface of the protruding silicon 13 (<10
The electrode may be drawn out to the 0> plane), the periphery of the protruding silicon may be filled with silicon oxide or silicon nitride grown in a vapor phase, the surface of the substrate is planarized, and then wiring using an aluminum film may be formed.

As is clear from the above description, in the semiconductor device according to the present invention, elements completely insulated from the substrate in both vertical and horizontal directions are formed in a crystal plane different from that of the substrate. Therefore, unlike the conventional structure, the present invention does not require any epitaxial layer and has an element region completely separated from the substrate, making it possible to construct a bipolar transistor with extremely high speed.

FIG. 8 is a cross-sectional structural diagram of a bipolar transistor showing another embodiment of the present invention. The silicon substrate 11 is an N-type silicon substrate with a <100> crystal plane as in the previous embodiment. In this embodiment, the surface of the silicon substrate 11 is 9
Reactive ion etching is performed to an arbitrary depth at an angle of 0° to form an emitter region 22 on the <010> plane and a high concentration region 20 on the <010> plane in the same manner as in the previous embodiment. In this example, the emitter and base regions 2
2.18 and high concentration collector region 20 are silicon substrate 1
1 and the element isolation region 17', and are formed perpendicularly thereto, there is an advantage that higher density of elements can be easily realized. In this embodiment, as in the previous embodiment, electrodes may be drawn out using doped polysilicon and wiring may be formed after planarization.

〔Effect of the invention〕

As explained in detail above, according to the present invention, by providing the emitter and base regions in a crystal plane different from the surface of the semiconductor substrate, epitaxial growth is not necessary and the same region as the epitaxial layer can be easily controlled. Furthermore, since the device region and the semiconductor substrate can be easily completely insulated and separated from each other, high-speed bipolar transistors can be easily achieved.

[Brief explanation of drawings]

1 to 7 are manufacturing process diagrams for clarifying a bipolar transistor structure showing one embodiment of the present invention,
FIG. 8 is a cross-sectional structural diagram of a bipolar transistor showing another embodiment of the present invention. 11...Silicon substrate, 13...Protruded silicon,
17.17'... Inter-element isolation region, 18... Base region, 20... High concentration collector region, 22... Emitter region, 23... Electrode. Kaya,, s porridge illustration

Claims (1)

[Claims] a semiconductor substrate; an emitter and base region provided on a crystal plane different from a crystal plane on the surface of the semiconductor substrate; a collector high concentration region provided on a complementary crystal plane of the crystal plane forming the emitter and base regions; 1. A semiconductor device comprising an element isolation region made of a substrate oxide film formed at a connection portion between one crystal plane and a substrate.