JPS63268253A - Insulating layer separating substrate and its manufacture - Google Patents
Insulating layer separating substrate and its manufactureInfo
- Publication number
- JPS63268253A JPS63268253A JP10232087A JP10232087A JPS63268253A JP S63268253 A JPS63268253 A JP S63268253A JP 10232087 A JP10232087 A JP 10232087A JP 10232087 A JP10232087 A JP 10232087A JP S63268253 A JPS63268253 A JP S63268253A
- Authority
- JP
- Japan
- Prior art keywords
- single crystal
- semiconductor single
- insulating layer
- layer
- region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 title claims description 37
- 238000004519 manufacturing process Methods 0.000 title claims description 18
- 239000004065 semiconductor Substances 0.000 claims abstract description 69
- 239000013078 crystal Substances 0.000 claims abstract description 62
- 239000000463 material Substances 0.000 claims abstract description 15
- 238000005530 etching Methods 0.000 claims abstract description 9
- 238000000034 method Methods 0.000 claims description 10
- 238000000926 separation method Methods 0.000 claims description 10
- 238000002955 isolation Methods 0.000 claims description 3
- 239000012535 impurity Substances 0.000 abstract description 14
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 5
- 229920005591 polysilicon Polymers 0.000 abstract description 5
- 229910052681 coesite Inorganic materials 0.000 abstract description 4
- 229910052906 cristobalite Inorganic materials 0.000 abstract description 4
- 229910052682 stishovite Inorganic materials 0.000 abstract description 4
- 229910052905 tridymite Inorganic materials 0.000 abstract description 4
- 235000012431 wafers Nutrition 0.000 abstract 6
- 239000000377 silicon dioxide Substances 0.000 abstract 3
- 235000012239 silicon dioxide Nutrition 0.000 abstract 3
- 239000007788 liquid Substances 0.000 abstract 2
- 230000001590 oxidative effect Effects 0.000 abstract 2
- 238000005498 polishing Methods 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 76
- 239000002356 single layer Substances 0.000 description 7
- 238000009792 diffusion process Methods 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000000347 anisotropic wet etching Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Landscapes
- Element Separation (AREA)
Abstract
Description
【発明の詳細な説明】 〔技術分野〕 この発明は絶縁層分離基板およびその製法に関する。[Detailed description of the invention] 〔Technical field〕 The present invention relates to an insulating layer-separated substrate and a method for manufacturing the same.
半導体素子の製造においては、酸化膜などの絶縁層（誘
電体層）により電気的に絶縁された島状領域を有する絶
縁層分離基板（ＤＩ基板）を作り、その島状領域に素子
を形成することが行われている。この島状領域は、単結
晶シリコンなど半導体結晶からなり、絶縁層を介してポ
リシリコンなどの支持体層で支持されている。In manufacturing semiconductor devices, an insulating layer separation substrate (DI substrate) having an island-like region electrically insulated by an insulating layer (dielectric layer) such as an oxide film is created, and elements are formed on the island-like region. things are being done. This island-like region is made of a semiconductor crystal such as single crystal silicon, and is supported by a support layer such as polysilicon through an insulating layer.
この絶縁層分離基板はつぎのようにして作成されている
。This insulating layer separated substrate is produced as follows.
第２図（ａｌにみるように、分離のための溝を形成する
個所以外を覆うマスク（ＳｉＯ□膜）２′が表面に施さ
れた半導体単結晶ウェハ素材１１′をエツチングし、第
２図山）にみるように、分離のための溝３′を形成した
半導体単結晶ウェハ１′を得る。溝３′を形成したのち
、第２図ｆｃｌにみるように、表面全体を絶縁層（Ｓｉ
Ｃ２）５′で覆う。ついで、絶縁層５′の上にポリシリ
コンからなる支持体層６′を形成した後、ウェハ１′の
裏面１′ａ側から溝３′の底部が露出するまで研磨すれ
ば、第２図（ｅ）にみるように、絶縁層５′で電気的に
分離された半導体単結晶島状領域１０″・・・１０″が
複数個形成された絶縁層分離基板が得られる。As shown in FIG. 2 (al), a semiconductor single crystal wafer material 11' whose surface is coated with a mask (SiO□ film) 2' covering areas other than those where grooves for isolation are to be formed is etched. A semiconductor single-crystal wafer 1' having grooves 3' for separation formed therein as shown in the ridge 1' is obtained. After forming the groove 3', the entire surface is covered with an insulating layer (Si
C2) Cover with 5'. Next, after forming a support layer 6' made of polysilicon on the insulating layer 5', the wafer 1' is polished from the back surface 1'a side until the bottom of the groove 3' is exposed. As shown in e), an insulating layer-separated substrate is obtained in which a plurality of semiconductor single crystal island regions 10''...10'' are electrically isolated by an insulating layer 5'.
ところで、この絶縁層分離基板では、島状領域１０“に
おける単結晶領域の厚みＬが、すべての島状領域１０“
・・・１０“で同じになっていた。そのため、異なる島
状領域１０″、１０”に形成される半導体素子の種類が
違う場合、素子の種類にかかわらず同じ厚みの半導体単
結晶領域を用いなければならない。つまり、その素子に
最適な厚みの半導体単結晶領域を用いることができない
ので、十分な特性を有する半導体素子を形成するのが困
難であるという問題があった。By the way, in this insulating layer separation substrate, the thickness L of the single crystal region in the island region 10" is equal to the thickness L of the single crystal region in the island region 10".
...10". Therefore, when the types of semiconductor elements formed in different island regions 10" and 10" are different, semiconductor single crystal regions of the same thickness are used regardless of the type of the elements. In other words, it is difficult to form a semiconductor element with sufficient characteristics because it is not possible to use a semiconductor single crystal region with an optimal thickness for the element.
この発明は、前記の事情に鑑み、異なる島状領域に形成
される半導体素子の種類が違う場合でも、十分な特性を
有する半導体素子を形成することができる絶縁層分離基
板およびその製法を提供することを目的とする。In view of the above-mentioned circumstances, the present invention provides an insulating layer-separated substrate and a method for manufacturing the same, which can form semiconductor elements with sufficient characteristics even when the types of semiconductor elements formed in different island regions are different. The purpose is to
前記目的を達成するため、第１の発明は、支持体層上に
絶縁層で電気的に分離された半導体単結晶島状領域が複
数設けられている絶縁層分離基板において、前記半導体
単結晶島状領域として、厚みの異なる複数種類の領域が
設けられていることを特徴とする絶縁層分離基板を要旨
とし、第２の発明は、分離のための溝で区画された複数
の領域を備え表面全体が絶縁層で覆われている半導体重
゛結晶ウェハを用い、前記絶縁層で電気的に分
離された半導体単結晶島状領域が複数設けられている絶
縁層分離基板を得るにあたり、前記半導体単結晶ウェハ
としては、厚みの異なる複数種類の区画領域の設けられ
ているものを用いることを特徴とする絶縁層分離基板の
製法を要旨とする。To achieve the above object, a first invention provides an insulating layer-separated substrate in which a plurality of semiconductor single crystal island regions electrically isolated by an insulating layer are provided on a support layer, in which the semiconductor single crystal islands The gist of the invention is an insulating layer separation substrate characterized in that a plurality of types of regions having different thicknesses are provided as the shape region, and a second invention is directed to an insulating layer separation substrate characterized in that a plurality of types of regions having different thicknesses are provided as the shape region. In order to obtain an insulating layer-separated substrate in which a plurality of semiconductor single crystal island regions electrically isolated by the insulating layer are provided using a semiconductor heavy crystal wafer that is entirely covered with an insulating layer, the semiconductor single crystal wafer is used. The gist of the present invention is a method for manufacturing an insulating layer-separated substrate, which is characterized in that a crystal wafer is provided with a plurality of types of divided regions having different thicknesses.
以下、この発明にかかる絶縁層分離基板およびその製法
を、その−例をあられす図面を参照しながら詳しく説明
する。DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, an insulating layer separated substrate and a method for manufacturing the same according to the present invention will be described in detail with reference to the accompanying drawings.
第１図（８１は、第１の発明にかかる絶縁層分離基板の
一実施例をあられす。FIG. 1 (81 shows an embodiment of the insulating layer separation substrate according to the first invention).
この絶縁層分離基板は、絶縁層（誘電体層）５で電気的
に分離された半導体単結晶島状領域１０．１０′を備え
ている。島状領域１０．１０′は支持体層６の上に形成
されている。島状領域１０における半導体単結晶領域の
厚みｌが島状領域１０′における半導体単結晶領域の厚
みβ′よりも厚くなっている。つまり、この絶縁層分離
基板では、半導体単結晶島状領域として、厚みの異なる
複数種類の領域が設けられているのである。This insulating layer-separated substrate includes semiconductor single crystal island regions 10 and 10' electrically isolated by an insulating layer (dielectric layer) 5. The island-like regions 10.10' are formed on the support layer 6. The thickness l of the semiconductor single crystal region in the island region 10 is thicker than the thickness β' of the semiconductor single crystal region in the island region 10'. In other words, in this insulating layer separated substrate, a plurality of types of regions having different thicknesses are provided as semiconductor single crystal island regions.
島状領域１０の半導体単結晶領域は、底側の不純物高濃
度層（Ｎ＋層）ｌｂと表面側の不純物低濃度層（Ｎ一層
）Ｉａの２層で構成されている。The semiconductor single crystal region of the island region 10 is composed of two layers: a high impurity concentration layer (N+ layer) Ib on the bottom side and a low impurity concentration layer (N single layer) Ia on the top side.
一方、島状領域１０′の半導体単結晶領域は、不純物低
濃度層（Ｎ一層）ｌａのみで構成されている。絶縁層５
は、例えば、Ｓ ｉ Ｏｚ膜で形成されているが、これ
に限らない。支持体層６は、例えば、ポリシリコンで形
成されているが、これに限らない。On the other hand, the semiconductor single crystal region of the island region 10' is composed only of a low impurity concentration layer (N single layer) la. Insulating layer 5
is formed of, for example, a SiOz film, but is not limited thereto. The support layer 6 is made of polysilicon, for example, but is not limited thereto.
このように、この絶縁層分離基板では、半導体単結晶島
状領域として、厚みの異なる複数種類の領域が設けられ
ている。そのため、例えば、異なる島状領域に形成され
る半導体素子の種類が違う場合でも、それぞれの素子に
適した厚みの半導体単結晶島状領域を備えた絶縁層分離
基板を用いて、十分な特性を有する半導体素子を、各島
状領域へ形成することができる。そして、特性が向上す
るだけでなく、例えば、厚みの薄い島状領域へ形成すれ
ばよい半導体素子の形成工程で、例えば、島状領域表面
から底に達する不純物領域の形成を行う場合、従来のよ
うに、半導体単結晶領域の厚みが選択できず、より厚い
島状領域に不純物領域の形成を行わなければならないと
したら、拡散処理時間が必要以上に長くなる。しかし、
これが、厚みの薄い島状領域が選択でき、ここに不純物
領域の形成を行う場合、不純物の拡散処理時間が短くて
すむ。つまり、半導体素子形成時間の短縮が図れる。In this manner, in this insulating layer separated substrate, a plurality of types of regions having different thicknesses are provided as semiconductor single crystal island regions. Therefore, for example, even if the types of semiconductor elements formed in different island regions are different, sufficient characteristics can be achieved by using an insulating layer-separated substrate with semiconductor single crystal island regions of thickness suitable for each element. A semiconductor element having the structure can be formed in each island region. In addition to improving the characteristics, for example, when forming an impurity region that reaches from the surface of the island region to the bottom in the process of forming a semiconductor element that only needs to be formed in a thin island region, the conventional If the thickness of the semiconductor single crystal region cannot be selected and the impurity region must be formed in a thicker island-like region, the diffusion processing time will be longer than necessary. but,
If a thin island region can be selected and an impurity region is formed there, the impurity diffusion processing time can be shortened. In other words, the time required to form a semiconductor element can be shortened.
この発明にかかる絶縁層分離基板は上記の実施例に限ら
ない。例えば、島状領域１０′も、島状領域１０と同様
複数の層で構成されていてもよい。層の構成も、Ｎ“層
とＮ一層の組み合わせに限らず、Ｎ層とＰ層、Ｐ層層と
Ｐ一層という組み合わせでもよい。もちろんこれらの層
が上下逆に積層されていてもよい。また、層の数も２層
に限らず、３層あるいはそれ以上であってもよい。また
、島状領域における半導体単結晶領域の厚みの種類も２
種類に限らず、３種類、あるいはそれ以上あってもよい
。半導体単結晶がシリコン単結晶以外の単結晶であって
もよい。The insulating layer-separated substrate according to the present invention is not limited to the above embodiments. For example, like the island region 10, the island region 10' may be composed of a plurality of layers. The structure of the layers is not limited to the combination of N'' layer and N single layer, but may also be a combination of N layer and P layer, or P layer and P single layer. Of course, these layers may be stacked upside down. , the number of layers is not limited to two, but may be three or more.Furthermore, the thickness of the semiconductor single crystal region in the island region may also be two.
The number of types is not limited, and there may be three or more types. The semiconductor single crystal may be a single crystal other than silicon single crystal.
続いて、第２の発明にかかる絶縁層分離基板の製法の一
例による基板の製造についての説明をする。Next, manufacturing of a substrate by an example of the method for manufacturing an insulating layer-separated substrate according to the second invention will be explained.
まず、第１図（ａ）にみるように、平板状の半導体単結
晶ウェハ素材１１の表面にマスク２を施す。First, as shown in FIG. 1(a), a mask 2 is applied to the surface of a flat semiconductor single crystal wafer material 11. As shown in FIG.
この半導体単結晶ウェハ素材１１は、不純物低濃度層（
Ｎ一層ｊｌ ａの上に不純物高濃度層（Ｎ”層）ｌｂを
エピタキシャル成長させた２層構成となっており、（１
００）面Ａを表面とする。マスク２は、分離のための溝
が形成される未マスク領域３を除いた部分を覆っており
、異なる複数種類のマスク厚みを有する。つまり、マス
ク２ａの個所は熱酸化によるＳｉｎ７層２１とこの上に
積層されたＣＶＤによるＳｉｎ、層２２からなり、マス
ク２ｂの個所はＣＶＤによるＳｉ０２層２２のみからな
る。This semiconductor single crystal wafer material 11 has a low impurity concentration layer (
It has a two-layer structure in which a high impurity concentration layer (N'' layer) lb is epitaxially grown on the N single layer jl a.
00) Surface A is the surface. The mask 2 covers a portion other than an unmasked region 3 where a groove for separation is formed, and has a plurality of different mask thicknesses. That is, the mask 2a consists of a thermally oxidized Sin7 layer 21 and the CVD Si layer 22 laminated thereon, and the mask 2b consists only of a CVD Si02 layer 22.
マスク２が施された半導体単結晶ウェハ素材１１に対し
て、例えば、ＫＯＨ液を用いて異方性ウェットエツチン
グを施す。まず、未マスク領域３がエツチングされ、第
１図（ｂｌにみるように、溝が形成されてゆく。ＳｉＯ
□層２２も、ウェハ素材１１よりはエツチングレートが
低いが、同時にエツチングされてゆき、ついには完全に
除去される。そうするとＳｉＯ□層２２のみが施されて
いた個所では、表面の（１００）面Ａがエツチング液に
さらされることになり、不純物高濃度層１ｂがエツチン
グされる。エツチング液にさらされた不純物高濃度層１
ｂが除去されるところまでエツチングを行い、第１図（
Ｃ１にみるように、（１１１）面Ｂがあられれている■
状の溝４で区画された複数の領域１ｇ・・・Ｉｇ’・・
・が形成された半導体単結晶ウェハ１が得られる。つい
で、第１図（ｄｌにみるように、このウェハ１表面全体
を絶縁層（熱酸化によるＳｉＯ□層）５で覆う。ウェハ
１における区画された領域１ｇでの半導体単結晶領域の
厚みは、領域１ｇ’での半導体単結晶領域の厚みよりも
薄くなっており、厚みの異なる複数種類の領域がウェハ
１に設けられているのである。つまり、分離のための溝
で区画された複数の領域を備え、表面全体が絶縁層で覆
われ、かつ厚みの異なる複数種類の区画領域の設けられ
ている半導体単結晶ウェハ１が得られるのである。Anisotropic wet etching is performed on the semiconductor single crystal wafer material 11 on which the mask 2 has been applied using, for example, a KOH solution. First, the unmasked area 3 is etched, and grooves are formed as shown in FIG.
Although the etching rate of the □ layer 22 is lower than that of the wafer material 11, it is etched at the same time and is finally completely removed. Then, in the area where only the SiO□ layer 22 was applied, the (100) plane A of the surface will be exposed to the etching solution, and the high impurity concentration layer 1b will be etched. High impurity concentration layer 1 exposed to etching solution
Etching is performed until b is removed, as shown in Figure 1 (
As seen in C1, the (111) side B is roughed ■
A plurality of regions 1g...Ig'... divided by grooves 4 in the shape of
A semiconductor single-crystal wafer 1 on which * is formed is obtained. Then, as shown in FIG. 1 (dl), the entire surface of this wafer 1 is covered with an insulating layer (SiO□ layer formed by thermal oxidation) 5. The thickness of the semiconductor single crystal region in the divided region 1g of the wafer 1 is: The thickness of the semiconductor single crystal region in the region 1g' is smaller than that of the semiconductor single crystal region, and multiple types of regions with different thicknesses are provided on the wafer 1. In other words, multiple regions partitioned by isolation grooves are provided. Thus, a semiconductor single crystal wafer 1 is obtained, the entire surface of which is covered with an insulating layer, and in which a plurality of types of partitioned regions having different thicknesses are provided.
つぎに、このウェハ１上に、第１図（ｄｌに一点鎖線で
示すように、ポリシリコンからなる支持体層６を形成し
た後、ウェハ１の裏面１ａ′から溝４の底が露出するま
で研磨する。そうすると、第１図ｔｅｌにみるように、
前に詳しく説明した半導体単結晶島状領域として厚みの
異なる複数種類の領域が設けられている絶縁層分離基板
が完成する。このようにして前述した利点を存する絶縁
層分離基板を得ることができるのである。また、格別に
特殊な工程を必要とするわけでもないので製造が容易で
ある。Next, after forming a support layer 6 made of polysilicon on this wafer 1, as shown by the dashed line in FIG. Polish it. Then, as shown in Figure 1,
An insulating layer separation substrate is completed in which a plurality of types of regions having different thicknesses are provided as the semiconductor single crystal island regions described in detail above. In this way, an insulating layer-separated substrate having the above-mentioned advantages can be obtained. Further, since no particularly special process is required, manufacturing is easy.
なお、前記の実施例では、半導体単結晶ウェハ素材１１
が、不純物低濃度層（Ｎ一層）ｌａの上に不純物高濃度
層（Ｎ”層）Ｉｂをエピタキシャル成長させた２層構成
となっていたので、完成した絶縁層分離基板の島状領域
１０を２層構成のものとすることができた。しかしなが
ら、半導体単結晶ウェハ素材は単一の層構成でもよいし
、３層以上の層構成でもよい。もちろんＮ層とＰ層とか
らなる層構成でもよい。複数の層構成の半導体単結晶ウ
ェハ素材を用いれば、領域内の単結晶層が複数の層構成
となっている島状領域を備えた絶縁層分離基板を得るこ
とが可能となる。In addition, in the above embodiment, the semiconductor single crystal wafer material 11
However, since it had a two-layer structure in which a high impurity concentration layer (N'' layer) Ib was epitaxially grown on a low impurity concentration layer (N single layer) la, the island-like region 10 of the completed insulating layer separation substrate was However, the semiconductor single crystal wafer material may have a single layer structure, or may have a layer structure of three or more layers.Of course, it may also have a layer structure consisting of an N layer and a P layer. By using a semiconductor single crystal wafer material having a plurality of layers, it is possible to obtain an insulating layer-separated substrate having an island-like region in which the single crystal layer within the region has a plurality of layers.
第２の発明にがかる絶縁層分離基板の製法は前記実施例
に限らない。エツチングもウェットエンチングに限らな
い。マスクの厚みを３種類以上にしておくと、マスク厚
みの薄い個所はど半導体単結晶ウェハ素材表面から深い
位置までエツチングされる。したがって、マスク厚みを
３種類以上にして、ウェハにおける区画された領域での
半導体単結晶領域の厚みの種類をマスク厚みの種類の数
だけ作ることができる。この場合、最終的に得られる絶
縁層分離基板では、半導体単結晶島状領域における厚み
の種類数を、マスク厚みの種類数と同じにすることがで
きる。The method for manufacturing the insulating layer-separated substrate according to the second invention is not limited to the above embodiment. Etching is not limited to wet etching. If there are three or more types of mask thickness, the areas where the mask thickness is thinner will be etched to a deeper position from the surface of the semiconductor single crystal wafer material. Therefore, by using three or more types of mask thicknesses, it is possible to create the number of types of thicknesses of the semiconductor single crystal regions in the partitioned regions of the wafer as many types of thicknesses as the number of types of mask thicknesses. In this case, in the finally obtained insulating layer separated substrate, the number of types of thickness in the semiconductor single crystal island region can be made the same as the number of types of mask thickness.
第１の発明にかかる絶縁層分離基板および第２の発明に
かかる製法で得られた絶縁層分離基板は、半導体単結晶
島状領域が複数設けられている構成において、前記半導
体単結晶島状領域として、厚みの異なる複数種類の領域
が設けられている。The insulating layer separated substrate according to the first invention and the insulating layer separated substrate obtained by the manufacturing method according to the second invention have a configuration in which a plurality of semiconductor single crystal island regions are provided, and the semiconductor single crystal island region As such, multiple types of regions having different thicknesses are provided.
そのため、異なる島状領域に形成される半導体素子の種
類が違う場合でも、十分な特性を有する半導体素子を形
成できる。また、半導体素子形成にあたっても、より適
切な製造条件とすることが可能となる。Therefore, even if the types of semiconductor elements formed in different island regions are different, semiconductor elements having sufficient characteristics can be formed. Furthermore, it is possible to use more appropriate manufacturing conditions when forming a semiconductor element.
【図面の簡単な説明】
第１図（ａ）〜（ｅ）は、第２の発明にかかる製法の一
例により絶縁層分離基板を製造する様子を工程順にあら
れしており、図（ａ）〜図（ｄｌは製造途中のウェハ素
材とウェハの断面図、図（ｅ）は完成した絶縁層分離基
板の断面図である。第２図（ａｌ〜（ｅｌは、従来製法
により絶縁層分離基板を製造する様子を工程順にあられ
しており、図（８１〜図（ｄ）は製造途中のウェハ素材
とウェハの断面図、図（ｅ）は完成した絶縁層分離基板
の断面図である。
１・・・半導体単結晶ウェハ １ｇ、Ｉｇ’・・・溝
で区画された複数の領域 ２・・・マスク ４・・
・溝 ５・・・絶縁層 ６・・・支持体層 １０
．１０′・・・半導体単結晶島状領域 １１・・・半
導体重結晶ウェハ素材[BRIEF DESCRIPTION OF THE DRAWINGS] FIGS. 1(a) to 1(e) show, in order of steps, how an insulating layer separated substrate is manufactured by an example of the manufacturing method according to the second invention. Figure (dl is a cross-sectional view of the wafer material and the wafer in the middle of manufacturing, Figure (e) is a cross-sectional view of the completed insulating layer separated substrate. The manufacturing process is shown in the order of steps; Figures (81 to d) are cross-sectional views of the wafer material and wafer during manufacture, and Figure (e) is a cross-sectional view of the completed insulating layer separated substrate. 1. ...Semiconductor single crystal wafer 1g, Ig'...Multiple regions divided by grooves 2...Mask 4...
・Groove 5...Insulating layer 6...Support layer 10
．． 10'...Semiconductor single crystal island region 11...Semiconductor heavy crystal wafer material
Claims (3)
単結晶島状領域が複数設けられている絶縁層分離基板に
おいて、前記半導体単結晶島状領域として、厚みの異な
る複数種類の領域が設けられていることを特徴とする絶
縁層分離基板。(1) In an insulating layer-separated substrate in which a plurality of semiconductor single-crystal island regions electrically isolated by an insulating layer are provided on a support layer, the semiconductor single-crystal island regions may include a plurality of types of semiconductor single-crystal island regions having different thicknesses. An insulating layer separated substrate characterized in that a region is provided.
面全体が絶縁層で覆われている半導体単結晶ウェハを用
い、前記絶縁層で電気的に分離された半導体単結晶島状
領域が複数設けられている絶縁層分離基板を得るにあた
り、前記半導体単結晶ウェハとしては、厚みの異なる複
数種類の区画領域の設けられているものを用いることを
特徴とする絶縁層分離基板の製法。(2) Using a semiconductor single crystal wafer having a plurality of regions partitioned by grooves for isolation and whose entire surface is covered with an insulating layer, semiconductor single crystal island regions are electrically separated by the insulating layer. A method for manufacturing an insulating layer-separated substrate, characterized in that the semiconductor single crystal wafer is used as the semiconductor single crystal wafer in which a plurality of types of divided regions having different thicknesses are provided.
るエッチング工程において、異なる複数種類の厚み個所
を有するマスクを表面に施した平板状半導体単結晶ウェ
ハ素材を、マスク厚みが薄く形成された個所ではウェハ
素材内まで達するように前記エッチングを施すことによ
り厚みの異なる複数種類の区画領域を形成する特許請求
の範囲第２項記載の絶縁層分離基板の製法。(3) A semiconductor single crystal wafer is a flat semiconductor single crystal wafer material whose surface is coated with a mask having multiple different thicknesses in the etching process to form grooves for separation. 3. The method of manufacturing an insulating layer-separated substrate according to claim 2, wherein the etching is performed so as to reach into the wafer material at the locations where a plurality of types of divided regions having different thicknesses are formed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10232087A JPS63268253A (en) | 1987-04-24 | 1987-04-24 | Insulating layer separating substrate and its manufacture |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10232087A JPS63268253A (en) | 1987-04-24 | 1987-04-24 | Insulating layer separating substrate and its manufacture |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63268253A true JPS63268253A (en) | 1988-11-04 |
Family
ID=14324275
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10232087A Pending JPS63268253A (en) | 1987-04-24 | 1987-04-24 | Insulating layer separating substrate and its manufacture |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63268253A (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6288334A (en) * | 1985-10-15 | 1987-04-22 | Nec Corp | Manufacture of dielectric insulation isolating substrate |
-
1987
- 1987-04-24 JP JP10232087A patent/JPS63268253A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6288334A (en) * | 1985-10-15 | 1987-04-22 | Nec Corp | Manufacture of dielectric insulation isolating substrate |
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