JPS6326885U - - Google Patents
Info
- Publication number
- JPS6326885U JPS6326885U JP12059186U JP12059186U JPS6326885U JP S6326885 U JPS6326885 U JP S6326885U JP 12059186 U JP12059186 U JP 12059186U JP 12059186 U JP12059186 U JP 12059186U JP S6326885 U JPS6326885 U JP S6326885U
- Authority
- JP
- Japan
- Prior art keywords
- display device
- parallel
- serial
- video
- displaying
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000015654 memory Effects 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 4
- 238000000034 method Methods 0.000 description 1
Landscapes
- Details Of Television Scanning (AREA)
Description
第１図は本考案の一実施例を示すデイスプレイ
装置のブロツク図、第２図はインターレース方式
による表示動作を説明するための説明図、第３図
は一般のデイスプレイ装置のブロツク図、第４図
は従来の太線化表示方式のデイスプレイ装置のブ
ロツク図である。
１：表示制御回路、２，２１，２２：ビデオメ
モリ、３，３１，３２：シフトレジスタ、４：Ｃ
ＲＴ、５：デイレイライン、６，８，９：ＯＲゲ
ート、７：インバータ。
FIG. 1 is a block diagram of a display device showing an embodiment of the present invention, FIG. 2 is an explanatory diagram for explaining display operation using the interlace method, FIG. 3 is a block diagram of a general display device, and FIG. 4 1 is a block diagram of a conventional thick-line display system display device. 1: Display control circuit, 2, 21, 22: Video memory, 3, 31, 32: Shift register, 4: C
RT, 5: Delay line, 6, 8, 9: OR gate, 7: Inverter.
Claims (1)
び奇数フイールド用のビデオメモリと、該各ビデ
オメモリに接続され、外部信号により独立にその
動作が制御されるパラレル―シリアル変換器と、
該各パラレル―シリアル変換器の出力を論理和演
算する手段と、該論理和演算する手段の出力を表
示する表示装置とを設けたことを特徴とするイン
ターレース方式デイスプレイ装置。 video memories for even and odd fields provided independently; a parallel-to-serial converter connected to each video memory and whose operation is independently controlled by an external signal;
An interlaced display device comprising means for performing an OR operation on the outputs of the respective parallel-to-serial converters, and a display device for displaying the output of the OR operation means.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12059186U JPS6326885U (en) | 1986-08-05 | 1986-08-05 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12059186U JPS6326885U (en) | 1986-08-05 | 1986-08-05 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6326885U true JPS6326885U (en) | 1988-02-22 |
Family
ID=31009048
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12059186U Pending JPS6326885U (en) | 1986-08-05 | 1986-08-05 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6326885U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0330203A (en) * | 1989-06-27 | 1991-02-08 | Matsushita Electric Works Ltd | Luminaire |
-
1986
- 1986-08-05 JP JP12059186U patent/JPS6326885U/ja active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0330203A (en) * | 1989-06-27 | 1991-02-08 | Matsushita Electric Works Ltd | Luminaire |
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