JPS6384183U

JPS6384183U -

Info

Publication number: JPS6384183U
Application number: JP17944986U
Authority: JP
Priority date: 1986-11-20
Filing date: 1986-11-20
Publication date: 1988-06-02

Description

[Brief explanation of the drawing]

第１図はこの考案の一実施例による倍走査表示
装置のブロツク図、第２図はこの考案によりＮＴ
ＳＣ（インターレース）方式の信号を倍速変換し
たときの画面構成図、第３図は従来の倍速インタ
ーレース変換のブロツク図、第４図は従来の方式
によりＮＴＳＣ（インターレース方式の信号を倍
速ノンインターレース変換したときの画面構成図
、第５図は従来装置のタイミングチヤートである
。図において、１ａ，１ｂは倍速変換用ライトメ
モリ、２，５はデイジタル遅延回路、３は加算回
路、４は１２倍回路、６はＤ／Ａ変換器、７はモ
ニター、８はライトメモリセレクタ、９はリード
メモリセレクタ、１１はフイールド切換セレクタ
である。なお、図中、同一符号は同一、または相当部分
を示す。 Figure 1 is a block diagram of a double scanning display device according to an embodiment of this invention, and Figure 2 is a block diagram of a double scanning display device according to an embodiment of this invention.
A screen configuration diagram when SC (interlaced) signals are converted to double speed. Figure 3 is a block diagram of conventional double speed interlace conversion. Figure 4 is a screen diagram of double speed non-interlaced conversion of NTSC (interlaced) signals using the conventional method. 5 is a timing chart of the conventional device. In the figure, 1a and 1b are write memories for double speed conversion, 2 and 5 are digital delay circuits, 3 is an adder circuit, 4 is a 12x circuit, 6 is a D/A converter, 7 is a monitor, 8 is a write memory selector, 9 is a read memory selector, and 11 is a field switching selector. In the drawings, the same reference numerals indicate the same or corresponding parts.

Claims

[Scope of utility model registration request]

A double scan display device comprising a font group having the same dot configuration in even and odd fields, and a data delay circuit for 12 horizontal scanning periods which is effective only in even fields after double speed conversion.