JPS63276902A - Hybrid coupler type semiconductor phase shifter - Google Patents

Abstract

PURPOSE:To obtain the miniaturized and lightweight titled semiconductor phase shifter by using a gate connection line so as to connect gates of two FETs of the phase shifter thereby using one bias circuit only. CONSTITUTION:A ground conductor 2 of a semiconductor substrate 1 is soldered to a chassis or the like to connect a common source electrode 8 and a grounding pad 16 to ground. A drive bias voltage is supplied from a bias pad 12 to a gate electrode 7 of one FET 9 and impressed also to a gate electrode 7 of the other FET 9 via a gate connection line 18. In this case, a common source electrode 8 is connected to ground and a drain electrode 6 is connected to ground in terms of DC by connecting the grounding pad 16 to ground and the two FETs 9 are operated normally. In connecting the gate electrodes of the two FETs in this way, one bias circuit is enough for the application to attain the miniaturized and lightweight phase shifter.

Description

[Detailed description of the invention] [Industrial application field] This invention is a child control antenna's phase control.

The present invention relates to reducing the size and weight of a hybrid coupler type semiconductor phase shifter used in applications, etc., and preventing characteristic deterioration in the event of bias circuit failure.

[Conventional technology]

FIG. 3 is a perspective view showing an example of a conventional hybrid coupler type phase shifter.
A semiconductor substrate such as aAs, (2) a ground conductor formed by metallizing a conductor such as gold on the bottom surface of the semiconductor substrate (1),
(3) is the main line of the phase shifter, (4) is the branch line hybrid coupler, (5) is the loading line added to the coupled output end and direct output end of the branch line hybrid coupler (4), respectively. 6) is the drain electrode of the field effect transistor (FFT), (7) is the gate electrode, (8) is the common source electrode of the two FETs, and (9) is the +
6) (7) +8). ac
i is a high impedance line of approximately 1/4 wavelength, 0 is approximately 4
1/1 wavelength low impedance line, 03 is a bias pad for receiving drive bias voltage from the outside, Q3 is ao (a distributed constant bias circuit that integrates 111Q3,
u4 is an impedance control line "R1I" of approximately 1/4 wavelength,
(F) is a low impedance Ivil path of approximately 1/4 wavelength, Q0 is a grounding pad, and the grounding bias circuit ′:c is added to the main line.

Next, the operation will be explained. The same driving bias voltage must always be applied to the two FB'l' (91).By switching this driving bias voltage between forward bias (oV) and reverse bias (minus several V), the Fg
The impedance of 'r(9) changes, the reflection phase seen from the branch line type hybrid coupler (4) to the loaded line (5) changes, and the transmission phase from the input to the output of the main line (3) changes, It operates so that the difference in transmission phase becomes a desired amount of phase shift. The ground conductor (2) is soldered to the chassis or the like and grounded. In the FBT (9), a driving bias voltage is applied from the distributed constant bias circuit (2) to the gate electrode (7), but in order to operate normally as an F'ET, the common source electrode (8) is made of gold wire or the like. The drain electrode (6) is grounded by grounding the grounding pad Ql with a gold wire or the like, and is set to the same voltage level as the ground conductor (2).

[Problem that the invention seeks to solve]

The conventional hybrid coupler type phase shifter has two
Two distributed constant bias circuits were used to apply the same drive bias voltage to the FETs (9). Therefore, there was a drawback that the chip size of the phase shifter became large. Also, if one of the two distributed constant bias circuits breaks down due to line breakage, etc., the two F'gT (91
There was a problem that the impedance of the phase shifter became unbalanced, causing insertion loss of the phase shifter and deterioration of vswa.

This invention was made to solve these problems, and aims to reduce the size and weight of the phase shifter by using only one distributed constant bias circuit that provides drive bias voltages to two FETs. Also. The present invention also aims to prevent insertion of a phase shifter, loss, and deterioration of vswa in the event that a distributed constant bias circuit fails due to a cut in the line or the like.

[Means to solve the problem’]

In the hybrid coupler type semiconductor phase shifter according to the present invention, one side of the single distributed constant bias circuit is omitted by connecting the gate electrodes of two FFs and Ts with conductive lines.

[Effect]

In this invention, the gate electrodes of two PETs are connected by a conductive line, so that when a drive bias voltage is applied to the gate electrode of one FET, both FETs are connected.
A bias is applied to T and it operates as a normal hybrid coupler type semiconductor phase shifter. Also, the bias circuit is
Even if the bias circuit fails due to line breakage, the amount of phase shift cannot be obtained, but there is almost no insertion loss or deterioration of the milk, and the influence on the surroundings can be kept to a minimum. .

[Embodiment] FIG. 1 is a perspective view showing an embodiment of the present invention. (1
) to aη are exactly the same as those of the above-mentioned conventional device. (to) is a gate contact #C line for connecting the gate electrodes (7) of two PgT (91) in a DC manner.

The figure shows only the substrate part of a hybrid coupler type semiconductor phase shifter. When used as a phase shifter, the semiconductor substrate (1) is soldered to a chassis etc. and connected to a ground conductor. (2) is grounded, and the common source electrode (8) and grounding pad uG are grounded with a gold wire or the like. Furthermore, the number of distributed arithmetic bias circuits u, which used to be two, is reduced to one.

In the hybrid coupler type semiconductor phase shifter configured as described above, the surface of the ground conductor (2) of the semiconductor substrate 111 is soldered to the chassis etc., and the common source electrode (8) and the ground pad Qe are connected to a gold wire or the like. After the bias pad υ is grounded, a driving bias voltage is supplied from outside, and the driving bias voltage is applied to the gate electrode (7) of one FgT (9).
) is applied to

At the same time, the drive bias voltage is also applied to the gate electrode (7) of the other F'ET (9) via the gate connection line 1iG). At this time, the common source electrode (8) is grounded and the drain electrode (6) is DC grounded by grounding the grounding pad αG, so the two f'ET
(91 operates normally.

By turning on and off this driving bias voltage, the impedances of the two F'gTs (9) change simultaneously, and the reflection phase of the loading line (5) as seen from the branch line hybrid coupler (4) changes. Since the reflection 1 phase at the coupled output end and the direct output end of the branch line type hybrid Kagura (4) changes, the transmission phase of the main line changes, and this difference is used as a phase shifter. Since the gate connection line (7) is used in this way, only one distributed constant bias circuit is required, and the phase shifter is made smaller and lighter.

Furthermore, even if the distributed constant bias circuit breaks down due to line breakage, etc., the impedance of the two PgTs (9+) will not become unbalanced, and no phase shift will be obtained (9)
Insertion loss and vswa deterioration can be prevented and the impact on the surrounding area can be minimized.

In the above embodiment, the bias circuit is a distributed constant bias circuit, but a lumped constant bias circuit using a resistor, a capacitor, and 4 may have the same effect.

FIG. 2 shows another embodiment of the present invention in which a lumped constant bias circuit is used as the bias circuit, and (1) to (9)
, Q2. αto1 is exactly the same as the previous embodiment of the present invention, oan is the resistor I (A), and a!n is the capacitor ground pad for grounding one electrode of the capacitor (A). , (2) is to (13,09-(2)).In this configuration, the capacitor ground pad Q
It is necessary to ground p with a gold wire, etc.

By reducing the number of lumped constant bias circuits to one, it not only becomes smaller and lighter, but also reduces the work of attaching gold wire by half. Although the above embodiment has been described using a branch line type hybrid coupler as an example, the present invention is not limited to this, and can also be applied to a phase shifter using an interdigital type hybrid coupler or a coupled line type hybrid coupler.

Further, in the above embodiment, a branch line is not added to the loading line, but the present invention can also be applied to a phase shifter having a configuration in which a branch line is added in parallel to the loading line.

Further, in the above description, the present invention has been described with respect to an example of the configuration of a single-bit phase shifter, but it goes without saying that it can also be applied to a configuration of a multi-bit phase shifter.

〔Effect of the invention〕

As explained above, this invention connects the gate electrodes of two FETs of a norhybrid coupler type semiconductor phase shifter with a gate connection line, so the bias circuit can be reduced to one, and the phase shifter can be made smaller and lighter. There is an effect.

In addition, even if the bias circuit fails due to a cut in the line, etc., the two F'ETs will be in the same state, so although the amount of phase shift will not be improved, insertion loss and deterioration of VS can be prevented. The impact on the surroundings can be kept to a minimum.

[Brief explanation of drawings]

FIG. 1 is a perspective view showing one embodiment of the hybrid coupler type semiconductor phase shifter of the present invention, FIG. 2 is a perspective view showing another embodiment of the hybrid coupler type semiconductor phase shifter of the present invention, and FIG. 1 is a perspective view showing an example of a conventional hybrid coupler type semiconductor phase shifter. In the figure, (1) is a semiconductor substrate, and (2) is a ground conductor. (3) is the main line E-3, (41 is the branch line type hybrid coupler, (5) is the loading line, (6) is the drain electrode, (7) is the gate electrode, (8) is the common source electrode,
(9) is FET, 00 is high impedance line, l is low impedance line, (2) is bias pad, Q3
is a distributed constant bias circuit, α4 is a high impedance line, (to) is a low impedance line, Qi is a grounding pad, Cη is a grounding bias circuit,
The circle is a resistor, (A) is a capacitor, 62υ is a capacitor ground pad, and (2) is a lumped constant bias circuit. Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (4)

[Claims] (1) A hybrid coupler consisting of a strip line formed on a semiconductor substrate, a main line connected to the input end and isolation end of the hybrid coupler, and connected to the first and second output ends of the hybrid coupler. A hybrid coupler type consisting of a loading line, a field effect transistor connected to the tip of the loading line, and a bias circuit composed of a strip line for applying a drive bias voltage to the gate electrode of the field effect transistor. In a semiconductor phase shifter, a single bias circuit is used to connect the gate electrodes of multiple field effect transistors with a conductive line and apply a driving bias voltage to the gate electrodes of multiple field effect transistors. A hybrid coupler type semiconductor phase shifter featuring: (2) The hybrid coupler type semiconductor phase shifter according to claim (1), wherein the bias circuit is composed of a resistor and a capacitor. (3) The hybrid coupler type semiconductor phase shifter according to claim (1), wherein the bias circuit is composed of a strip line and a capacitor. (4) Claims (1) and (2) include a branch line added in parallel to the loading line connected to the first and second output ends of the hybrid coupler.
) or the hybrid coupler type semiconductor phase shifter described in item (3).