JPS6329445B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an automatic equalizer, in particular, an automatic equalizer that multiplies successive sample signals by coefficients and adds them, and controls the coefficients of each sample according to the state of the output signal to achieve a predetermined equalization. This relates to an automatic equalizer that obtains characteristics.

When transmitting data using a telephone line or the like, signal amplitude distortion, delay distortion, etc. occur depending on the characteristics of the telephone line. To compensate for this, an equalizer is used at the input of the repeater or receiver. In particular, when the transmission signal is a pulse signal or sample signal and the characteristics of the transmission line fluctuate due to external conditions (e.g. temperature or line switching), this fluctuation can be quickly detected and the characteristics of the equalizer can be adjusted. An automatic equalizer that adapts to the transmission line is required.

As such an automatic equalizer, one having the configuration shown in FIG. 1 is known. In the same figure, x _i (i=
n-N to n+N) are sample values subjected to telephone line distortion, 2 is a delay element with a delay time of one sample period, 3 c _i (i=-N to +N) is an adjustable tap coefficient, 4 is an adder, y _o = _N 〓 ^j=N c _i x _oi ……(1)
generates the output of 6 is a discriminator, and y _D indicates the discrimination result. 8 is a circuit for multiplying by tap adjustment coefficient g. Adjustment of each tap coefficient is done using 9 multipliers and 10 multipliers.
is executed according to the following equation (2) using the subtractor.

c ^(m+1) _i = c ^(m) _i −g・x _oi・(y _o −y _D )……(2
) Here, m means the m-th adjustment.

On the other hand, in recent years there has been a growing movement to implement processing in communication equipment using high-speed microprocessors, and automatic equalizers are one example of this. However, in order to implement equations (1) and (2) with a microprocessor, the number of multiplications per sample time is 3×
(2N+1) times are required. Taking the case of CCITT Recommendation V.29 as an example, the sampling time is 416 μs and the number of multiplications is a two-dimensional automatic equalizer in V.29 (there are two tap coefficients for each of data 3 and 1 in Figure 1). 6×(2N+1) times are required.
Further, the value of N is approximately 30, and one multiplication must be performed within approximately 1 μs. This calculation time is approximately the limit value of microprocessors currently available on the market, and it is impossible to execute other functions in parallel.

Therefore, it is an object of the present invention to provide an automatic equalizer that eliminates the above-mentioned drawbacks of the prior art, reduces the amount of calculations, and achieves substantially the same equalization characteristics as conventional equalizers. .

In order to achieve the above object, the present invention is characterized in that a circuit for adjusting the tap coefficient of each sample value is configured to adjust the tap coefficient for each sample period. As described in the example below, an example of a form in which adjustment is performed for each multiple sample period is a case in which even-numbered taps and odd-numbered taps are performed alternately in each sample period, that is, a specific tap is Tap adjustment will be performed every sample period. That is, in the present invention, a plurality of tap coefficient adjustment circuits that adjust the tap coefficient of each sample value are divided into multiple groups (in the above example, two groups, an even numbered number and an odd numbered number), and these multiple groups The tap coefficients of the selected groups are selected cyclically and sequentially at a cycle (in the case of the above two groups, they are selected alternately at a sample cycle), and the tap coefficients of the selected group are calculated at one sample cycle. The tap coefficients in a group are controlled to be updated every multiple sample periods (in the case of the above two groups, two sample periods).

Therefore, the number of calculations is significantly reduced, and experiments have shown that equalization characteristics that are substantially the same as those of conventional automatic equalizers that control the coefficients for each sample period have been found. .

The present invention will be explained in detail below with reference to Examples.

FIG. 2 is a circuit diagram showing the configuration of an embodiment of the automatic equalizer according to the present invention, which is basically the same as that shown in FIG. 1 except for the tap coefficient adjustment circuit. From an input terminal 1, a sample signal having a sample value x _i is sent to a plurality of cascaded delay elements 2+N, 2+N-, each having a delay time of a sample period.
1, ..., 2-N+1. The input/output section (tap) of each delay element includes multipliers 3+N, 3+
N-1,..., 3-N; 9+N, 9+N-1,...
..., 9-N; subtractor 10+N, 10+N-1, ...,
A tap coefficient adjustment circuit consisting of 10-N is provided,
The outputs of each tap coefficient adjustment circuit are summed by an adder 4 to output an automatically equalized output signal y _o .

A part of this output signal y _o is sent to a discriminating circuit 6 which discriminates which of the predetermined signals the sample signal is, and outputs the discriminated discriminating circuit y _D.
A subtracter 7 calculates the difference between the output signal y _O and the identification signal y _D , and the output thereof is multiplied by a coefficient g (a value smaller than 1) in a multiplier 8. The output of the multiplier 8 is alternately distributed to the two lines 5-1 and 5-2 every sampling period by the switch circuit 5, and the signal g·(y _o −y _D ) distributed to the line 5-1 is as described above. It is multiplied by the sample signal (xo _-2l ) in the even-numbered multiplier 9 of the tap coefficient adjustment circuits. Also, the signal g.(y _o -y _D ) distributed to the line 5-2 is converted into a sample signal (x _o-2l-1 ) by the multiplier 9 of the odd-numbered tap coefficient adjustment circuit.
is multiplied by The subtracter 10 calculates the difference between the outputs of these multiplier circuits 9 and the coefficients from the previous multiplier 3 (i.e. even-numbered coefficients c ^2m-2 _2l , odd-numbered coefficients c ^2m-1 _2l+1 ). and add this to multiplier 3 as a new coefficient. Therefore, the even numbered (2l) multiplier 3's
The 2mth coefficient c ^2m _2l and the 2m+1st coefficient c ^2m+1 _2l+1 of the odd-numbered ( ₂ l+1) multiplier 3 are c ^2m _2l = c ^2m-2 _2l −g・x _o-2l, respectively. (y _o −y _D )……(3) c ^2m+1 _2l+1 ＝c ^2m-1 _2l+1 −g・x _o-2l-1 (y _o −y _D )……(4) . Also, use the previous coefficient c ^2m _2l for the odd-numbered coefficient of the even-numbered multiplier 3, and use the previous coefficient c ^2m+1 _2l+1 for the even-numbered coefficient of the odd-numbered multiplier 3. become. In this way, the number of multiplications required for each sampling time of the automatic equalizer is 2×(2N+
1) and will be reduced to 2/3 of the previous level. Therefore, it is not necessary to use high-speed component circuits.

FIG. 3 is a diagram comparing the effects of the conventional automatic equalizer and the embodiment shown in FIG. ), and in the figure, the □ marks are based on the embodiment of the present invention, and the x marks are based on conventional automatic equalization. The number of taps of the automatic equalizer is 32, and the multiplier g (tap update gain) is 0.0005.

As is clear from the figure, after approximately 10,000 tap updates, the relative value of the sum of squared errors becomes almost equal to that of the conventional one.

Although the present invention has been described above using Examples, the present invention is not limited to the above Examples. For example, as shown in FIG. 4, a writable memory (RAM) 11 that stores data (Xn-i) having a tap coefficient C _i and distortion for each sampling interval;
a read-only memory (ROM) 12 for storing identification and judgment thresholds ( _yD ); an addition/subtraction circuit 14;
A multiplier 13 that updates some of the tap coefficients every sampling period is prepared, and these are used in the above-mentioned (3).
A control circuit 15 controlled by an automatic equalization algorithm expressed by equation (4) can be provided, and the configuration can be configured to perform substantially the same operation as the embodiment described above.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram of a conventional automatic equalizer, FIGS. 2 and 4 are diagrams showing the configuration of an embodiment of an automatic equalizer according to the present invention, and FIG. 3 is a diagram showing the configuration of an embodiment of an automatic equalizer according to the present invention. FIG. 7 is a diagram showing the relationship between the number of tap updates and error for comparing the effects of the automatic equalizer of the embodiment. 1...Input terminal, 2...Delay element, 3, 8, 9
... Multiplier, 4 ... Adder, 5, 11 ... Switch circuit, 6 ... Discrimination circuit, 7, 10 ... Subtractor.

Claims (1)

[Claims] 1. It has an arithmetic circuit that multiplies each of a plurality of consecutive input sample signals by a coefficient, adds each sample signal multiplied by the above coefficient to output it, and uses the added output to obtain the above coefficient. In the automation device, the calculation means and the coefficient multiplication means divide the plurality of input sample signals into a plurality of groups, and cyclically process the plurality of sample signal groups divided into the plurality of groups at a sampling period. and performs an operation of multiplying the sampling signal of the selected group by a coefficient during the sampling period, and the coefficient is updated every sampling period that is a multiple of the number of the groups. An automatic equalizer characterized by: