JPS6329793A - Graphic processing device - Google Patents

Abstract

(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a graphic processing device suitable for use in a color display device using a cathode ray tube (CRT), and more particularly, to a graphic processing device using a look-up table. Regarding.

[Conventional technology]

For CRT color display devices, a graphic processing device is used to
Some devices are equipped with a memory that stores a look-up table (hereinafter referred to as LUT) for color information to be displayed on the T screen. In this LUT memory, different color information is sequentially stored at different addresses, and by specifying this address, the desired color information stored at this address is read out and supplied to the CRT to display the desired color information. Colors are displayed on the screen. The graphic processing device is also provided with an image memory. This image memory contains
An address is assigned to each pixel on the CRT, and each address contains the address (in the LUT memory) for the color to be displayed by the pixel on the CRT screen.
(hereinafter referred to as pixel data) is stored.

As the CRT scans, addresses in the image memory corresponding to the scan positions are sequentially specified and pixel data is read out. With these pixel data, LU
Color information for the scan position is read from the T memory. This causes colors to be displayed on the CRT screen.

LUTs can be used to increase the number of apparent colors, and can also be used without changing the contents of image memory.
It is possible to quickly change the color to be displayed simply by rewriting the contents of , and for this reason it is used in many display devices.

By the way, if you want to change the displayed color, you can simply rewrite the contents of the LUT, but if there is a rewriting request, this rewriting will be performed even during the CRT scan period.
This is performed while displaying colors on the screen, that is, while reading color information from the LOT memory. In this way, the rewriting is done at the same time as the request, and the CR
This is to avoid interruption of color display on the T screen.

However, when rewriting the contents of the LUT, the address of the LUT memory where new color information is written is specified, but since this specified address is fixed, this newly written color information is not displayed on the screen. This will appear as noise.

To eliminate this problem, rElectronic D
esignJSep5.1985pp・131-140
It has been proposed to configure the LUT memory with a dual port memory, as disclosed in .

[Problems to be solved by invention]

However, in the conventional technology as described above, the L for the currently displayed pixel is
If the UT memory read address (i.e., pixel data) and the LUT memory address to which new color information is written are different, no noise will occur on the CRT screen, but if the two addresses match, Noise still appears on the CRT screen.

SUMMARY OF THE INVENTION An object of the present invention is to provide a graphic processing device that solves the above problems and allows rewriting in an LUT memory without noise appearing on the screen.

[Means for solving problems]

In order to achieve the above object, the present invention provides means for holding new contents to be written to the LUT memory, and
The contents of the holding means are written into the 1LUT memory during the retrace period.

[Effect]

Since the LOT is rewritten during the retrace period of the CRT, the pixel data from the image memory and the specified address of the LUT memory for writing do not match.
Therefore, no noise occurs on the CRT screen due to rewriting of the LUT memory.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a graphic processing device according to the present invention, in which 100 is a microprocessor 1=+l−
(MPU), 110 is an image memory, 120 is a selector, 130 is an LUT memory, 140 is a digital/analog (D/A) converter, 150 is a CRT, 160 is an LUT conversion circuit, 200°210 is a latch, 220 to 2
50 is a D-type flip-flop (FF), 260 is an AND gate, and 270 is a clock generator.

In the figure, an LUT is stored in the LUT memory 130, and different color information forming the LUT is stored at different addresses. Furthermore, in the image memory 110,
An address is assigned to each pixel of the CRT 150, and each address contains the address of the LUT memory 130 for the color to be displayed by the pixel (i.e.
pixel data) is stored.

When displaying an image on the CRT 150, the MPU 100 scans the address line 1 while scanning the CRT 150.
The address for the pixel at the scan position is sent to the image memory 110 via 01, and the pixel data for that pixel is read from there. At this time, LUT
Each of the FFs 220 to 250 of the conversion circuit 160 is cleared, and each output is "O". The output of the FF 230 is supplied as a selection signal to the selector 120 via the signal line 231, and when this is 170 +#, the selector 120 selects the output of the image memory 110 and sends it to the LUT memory 130. Furthermore, the “0” output of the FF 240 is sent to the LUT as a write enable signal via the signal line 241.
The data is sent to memory 130.

At this time, LUT memory 130 is set to read mode.

Therefore, each pixel data read from the image memory 110 is supplied to the LUT memory 130 via the selector 120. As a result, from the LUT memory 130, C
Color information is read out for each pixel scanned by the RT 150, converted into an analog signal by the D/A converter 140, and supplied to the CRT 150. This allows CRT
Color display is performed on the screen of 150.

Note that during the retrace period of the CRT 150, a blanking signal of "1" is output from the MPU 100 to the signal line 104. As a result, the D/A converter 140 stops operating during this retrace period.

Next, the LUT rewriting operation in the LUT memory 130 will be explained using FIG. 2.

When rewriting is requested, the MPU 100
A write address signal representing the address to be rewritten in the LUT memory 130 is output to the data line 10.
Output the write data to 3.

At the same time, the MPU 100 also outputs a LUT set signal to the signal line 105, whereby the write address signal is temporarily stored in the latch 200 and the write data is stored in the latch 210, respectively.

The LUT set signal also becomes the C (clock) input of the FF 220, and thereby the FF 220 takes in the C input of "1". Therefore, the output of the FF 220 becomes "1" (hereinafter referred to as the FF being set), and the AND gate 260 is turned on. After that, MPU 1
00 outputs a blanking signal of "1" to the signal line 104, this blanking signal passes through the AND gate 260 and is supplied to the FF 230 as a C input. On the other hand, the clock φ output from the clock generator 270 to the signal line 271 is supplied to the FFs 230 to 250 as a C input, and at the rising edge of the clock φ, the FF 230 takes in the blanking signal and is set, and its output is inverted from 440 II to '1''. This causes the selector 120 to select the output of the latch 200, and the write address signal is LOT instead of the pixel data.
A memory 130 is provided.

Furthermore, the FF 240 is set by the output of Ll 113 of the FF 230 at the next rising edge of the clock φ, and its output becomes "I 11". As a result, the write enable signal becomes "1" and the LUT memory 130 The write mode is entered, and the write data stored in the latch 210 is L.
It is written to the address specified by the write address signal of the UT memory 130.

Further, due to the output of "1" from the FF 240, the FF 250 is set at the next rising edge of the clock φ, and its output becomes "1''. As a result, FF220,2
40 are cleared and their outputs become “0”, and the LU
The T memory 130 is again in read mode. and,
Since the output of the AND gate 260 becomes "0", the output of the FF 230 becomes ll at the next falling edge of the clock φ.
became O11 (hereinafter referred to as "reset")
, the selector 120 selects the output of the image memory 110, and the reading of color information from the LUT memory is started again.

Incidentally, when the output of the FF 240 becomes OII, the FF 250 is reset at the next rising edge of the clock φ, and therefore the FFs 220 to 250 are set to their original states (initial states).

As described above, in this embodiment, even if there is a request to rewrite the LUT memory 130 while the CRT 150 is scanning, this rewriting is performed during the retrace period of the CRT 150, and noise appears on the screen of the CRT 150. will not occur.

FIG. 3 is a block diagram showing another embodiment of the graphic processing device according to the present invention, in which 300 is a LUT rewriting memory;
10 is a counter, 320 is a selector, 330 is a detection circuit, 340 is an FF, 350 is an AND gate, 360 is an FF
, 370 is an AND gate, 380 is an inverter,
Parts corresponding to those in FIG. 1 are given the same reference numerals.

The operation of this embodiment will be explained below with reference to FIG.

When displaying on CRT150, FF220-250
and FF340, 360 are in a cleared initial state, and the outputs of FF220 to 250 and FF340 are “0”.
'', the Q output of the FF 360 is "O", and the Q output is 41''. The Q output of this FF 360 is supplied as a selection signal to the selectors 120 and 320 via the signal 1!361, and is also inverted by the inverter 380 and then
60 and the reset terminal R of the counter 310.

When this selection signal is 110N, selector 120
selects the output of the image memory 110, and the selector 320 selects the output of the latch 200. Further, the output of the AND gate 370 is supplied to the LUT memory 130 as a write enable signal and to the counter 310 as a clock via a signal line 371. At this time, FF360's Q
Since the output is 50", the output of the AND gate 370 is also "0" and the Lt)T memory 130 is in the read mode. Therefore, similar to the embodiment of FIG. Color information is read from the LUT memory 130 according to the data, and color display is performed on the CRT 150.

Next, when there is a request to rewrite the LUT memory 130, the MPU
The write address signal and write data output from 100 are stored in latches 200 and 21Q, respectively, and the signal 1
FF22 by LUT set signal via i1105
It is set to 0 and its output is 141 It. Also, at this time, the FF 360 is in the initial state, its Q output is "0", and the output of the inverter 380 is "1", so the output of the FF 220 becomes "1", and immediately after that, p
The FF 230 is set at the rising edge of the clock φ.

Therefore, at the next rising edge of clock φ, FF24
Also set to 0. As a result, LUT rewriting memory 3
The write enable signal of 00 becomes "1", which becomes the write mode, and the write data stored in the latch 210 is written to the address specified by the write address signal stored in the latch 200.

Furthermore, FF340 is set by the output of "1" from FF240, and FF240 is set at the next rising edge of clock φ.
Also set to 0. By this, FF220, 240
is cleared. Furthermore, as in the case of FIG.
230 and 250 are also cleared. By clearing the FF 240, the write enable signal of the LUT rewriting memory 300 becomes #Ou, and the memory 300 enters the read state. Therefore, from the LUT rewriting memory 300, the write address signal stored in the latch 200 becomes a read signal, and the written data is read out and supplied to the LUT memory 130 through the data line 301. . However, since LUT memory 130 is in read mode, this data is not written.

As described above, at the same time as data is written to the LUT rewriting memory 300, the FF 340 is set and its output becomes "1". After that, the signal m104 is sent from the MPU 100.
When a blanking signal of ``1'' is supplied via
This blanking signal is passed through AND gate 350 to F
It is supplied to F360, and at the same time FF360 is set and its Q output is "1", -φ- ratio output 110 It
bawl. The FF 340 is reset at the falling edge of this output.

When the Q output of FF360 becomes "1"', selector 12
0,321 selects the counter value output from the counter 310 to the data line 311 as the write address signal, and the output of the inverter 380 becomes it OIt, turning off the AND gate 260, and The counter 310 is reset at the edge. Furthermore, F
When the Q output of F360 becomes “1”, the AND gate 370 turns on, and the clock generator 270
The clock φ is supplied to the LUT memory 130 as a write enable signal and to the counter 310 as a clock via an AND gate 370, respectively.

The LUT memory 130 is in write mode when the write enable signal is "1", and the counter 310 counts up by 1 at the falling edge of the clock.

Therefore, when the first "1" clock φ is output from the AND gate 370, the LUT memory 130 enters the write mode during the period of the clock φ. At this time, the counter 31
The count value of 0 is O, and address 0 is designated for both the LUT memory 130 and the LUT rewriting memory 300. Therefore, the data at address 0 is read in the LUT rewriting memory 300, and this data is transferred to the LUT memory 130.
is written to address 0.

At the falling edge of this first clock φ, the counter 31
The count value of 0 becomes 1, and when the next clock φ is output from the AND gate 370, the data at address 1 of the LUT rewriting memory 300 is read out and stored in the LUT.
It is written to address 1 in memory 130. Similarly, each time the clock φ passes through the AND gate 370, the LUT
Data is read from the rewrite memory 300 in address order and sequentially written to the same address in the LUT memory 130.

The count value of counter 310 is also supplied to detection circuit 330. This detection circuit 330 detects that this count value is LU
T memory 130. When the number is one more than the final address of the LUT rewrite memory 300, that is, when all data has been rewritten from the LUT rewrite memory 300 to the LOT memory 130, a reset signal is generated in the signal a331, Reset FF360. For example, when the LUT memory 130 and the LUT rewriting memory 330 have a capacity to store four types of color information, the count value of the counter 310 is 3-bit data, which is a binary number representing 5 in decimal. (101) When it becomes 2, the detection circuit 33
A reset signal is generated from 0. As a result, the selector 120 selects the output of the image memory 110, the AND gate 370 is turned off, and the LUT memory 130 is fixed in the read mode. Therefore, when the retrace period ends, color display on the CRT 150 starts again. At this time, the LUTs in the LUT memory 130 and the LUT rewriting memory 300 are the same.

As described above, in this embodiment, when there is an LUT rewriting command, the LUT is first rewritten in the LUT rewriting memory 300 at the same time as this command, and the LUT rewriting memory is rewritten during the blanking period of the CRT 150. 300 is written to the LUT memory 130, and as a result, the LUT memory 13
This rewrites the LUT of 0. Therefore, in this embodiment as well, no noise occurs on the CRT screen even if the LUT is rewritten.

〔Effect of the invention〕

As explained above, according to the present invention, no matter when there is a request to change the contents of the LUT, this is always executed during the retrace period of the CRT, so that the pixel data and the writing in the LUT memory are Lt
You can change the contents of JT.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the graphic processing device according to the present invention, FIG. 2 is a timing chart showing its operation, and FIG. 3 is a block diagram showing another embodiment of the graphic processing device according to the present invention. FIG. 4 is a timing chart showing the operation. 110... Image memory, 120... Selector, 13
0... Lookup table memory, 150... Cathode ray tube, 160... Lookup table changing circuit. 200.210-latch, 220-250 = D type flip-flop, 260...AND gate, 300...
- Lookup table rewriting memory, 310... Counter, 320... Selector, 330... Detection circuit, 340... D type flip-flop, 350... AND gate, 360... D type flip flop. 370...AND gate, 380...Inverter.

Claims (1)

[Claims] 1. An image memory that stores pixel data for each pixel of a cathode ray tube, and a lookup table memory that stores a lookup table consisting of color information to be displayed on the cathode ray tube. In a graphics processing device that reads color information from the look-up table memory based on pixel data and displays colors on the screen of the cathode ray tube, a first means for storing write data together with a write request; second means for detecting a retrace period of the tube; and third means for writing write data stored in the first means during the retrace period by the second means into the look-up table memory. A graphic processing device characterized by being provided with.