JPS63299517A - Binary/ternary converting circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention is applicable to binary-value signals used for communication in integrated circuits (ICs), etc.
This relates to a three-value conversion circuit.

2. Description of the Related Art In recent years, ternary signals, which are more efficient than binary signals, have come to be used for communication between ICs. By using ternary signals, the number of wires between ICs can be reduced.

Since processing is performed in binary within the IC, binary-to-ternary conversion must be performed when outputting the processing results.

FIG. 3 is a circuit diagram showing a conventional binary-to-ternary conversion circuit, where 1 is an input terminal to which the first binary signal (Do) is input, and 2 is the input terminal for the second binary signal (Dl). ) is the input terminal. 3 is an inverter, and input terminal 1 is used as an input.
is connected. 4 is NO+'? Gate and NO
The first input terminal 401 of the R gate 4 is connected to the input terminal 1, and the second input terminal 402 is connected to the input terminal 2. 5 is a NAND gate; The output terminal of the inverter 3 is connected to the input terminal 501 of the inverter 3, and the input terminal 2 is connected to the input terminal 502 of the inverter 3. 6 is a P-channel FET, and the output terminal of the NAND gate 5 is connected to the gate electrode. 7
is an N-channel FET, and the gate electrode has a NOR
The output terminal of gate 4 is connected. P channel F
The source terminal of ET6 and the source terminal of N channel are the first
power supply terminal 8 (V, , ) and second power supply terminal 9 (vSs)
are connected to each. The drain of P-channel FET6 and the drain of N-channel FET7 are connected,
Resistors 10 and 11 having the same resistance value are connected between the source and drain of each FET. Both FE7
6.7 connection point and output terminal 12 are connected, output terminal 1
A 2- to 3-value signal is output.

The operation of the binary-to-ternary conversion circuit configured as described above will be explained below.

First, input signal D0. of input terminal 1.2. When D is "Lo" and "Lo" respectively, the output signal of the inverter 3 is "H" and the input signal of the NAND gate 5 is "H".
Since it becomes “L”, the output signal is “Lo”.Here, “
Ho is at the same level as the first power supply terminal 8. , L゛ is the second one! Apply Vss at the same level as source terminal 9.

As a result, P-channel FET 6 is turned off. Since the input signals of the NOR gate 4 are L and "Lo," the output signal becomes "Ho" and the N-channel FET 7 is turned on, and the output signal outputted to the output terminal 12 becomes "Lo."

Therefore, input signal D0. D.

When each is “Lo,” the output signal of the output terminal 12 is “
It becomes Lo.

Next, the input signal D0 of input terminal 1 is “Ho, input terminal 2
When the input signal D1 is L°, the output signal of the NAND gate 5 is "Ho", so the P-channel FET 6 is off.The input signal of the NOR gate 4 is "Ho, "
Since it becomes Lo, the output signal becomes "Lo" and N-channel FET 7 is also turned off. Therefore, both FETs 6 and 7 are turned off, so the level of the signal output from output terminal 12 is determined by the resistance connected between power supply terminals 8 and 9. 10.11, and since the resistance values of the resistors 10.11 and 10.11 are the same, the level of the output signal is v, Dl2. That is, the "Mo level" which is the intermediate potential level is output.

Furthermore, the human input signal D0 at the input terminal l is °L°.

When the input signal D1 of input terminal 2 is “H”, NA
Since the input signals of the ND gates 5 each become "Ho", the output signals become "Lo" level, and the P-channel FET
6 is turned on. Since the human input signals of NOR gate 4 are 'L' and 'H', the output signal is L°, N-channel FET 7 is turned off, and output terminal 1 is turned off.
The output signal output to 2 becomes "Ho". Therefore, the input signal is .

When Dl is "H" at "L", the output signal of the output terminal 12 becomes "H".

Next, input signal of input terminal 1. is “Ho, input terminal 2
When the input signal D1 is “Ho”, the NΔND gate 1-
The input signal of FET 5 becomes "Lo, H°" and the output signal becomes "Ho", so the P-channel FET 6 is turned off. Since the input signals of the NOR gate 4 are respectively °H'', the output signals are °L'' and the N-channel FET
7 is also turned off and the output signal is determined by resistor 10.11 and becomes M°.

From the following operations, the relationship between the level of the signal input to the input terminal 1.2 and the level of the output signal output from the output terminal 12 can be summarized as shown in Table 1.

Table 1 Problems to be Solved by the Invention However, in the above configuration, a resistor is connected to the output terminal, so if there are multiple binary-to-ternary conversion circuits, the °M'' output cannot be determined. However, a resistor is required for each output terminal.Furthermore, there is a problem in that the input impedance on the side receiving the ternary output must be larger than the resistor that determines the ternary output.

In view of the above-mentioned problems, the present invention has been developed without connecting a resistor to the output terminal of the binary-to-ternary conversion circuit.

A binary-to-ternary conversion circuit capable of outputting levels is provided.

Means for Solving the Problems In order to solve the above problems, the binary-to-ternary conversion circuit of the present invention includes an AND gate to which a first binary signal is supplied to a first input terminal; a first inverter whose input terminal is supplied with two binary signals; an output of the first inverter is supplied to a second input terminal of the AND gate; and an output terminal of the AND gate is an enable terminal; a tri-state buffer connected to and having the second binary signal supplied to its input terminal; a second inverter having an input terminal connected to the output terminal of the AND gate; a voltage source that generates a potential; an analog switch in which the output terminal of the second inverter is connected to a switch switching terminal and the output terminal of the voltage source is connected to an input terminal; an output terminal of the tri-state buffer and the analog switch; It is characterized in that the output terminals of the switch are connected and an output is generated from the connection point.

Operation With the above-described configuration, the present invention outputs the second binary input signal D1 from the tri-state buffer, and the L' and 'H' outputs of the binary-to-ternary conversion circuit are set to the potential at the midpoint of the "M° small output". Since the output of the voltage source that generates M° is outputted via an analog switch, it is possible to configure a binary-to-ternary conversion circuit to determine a small output without connecting a resistor to the output terminal. . In addition, the conversion from binary to 3 (li!) requires a simple circuit configuration since the second binary input signal D1 is outputted only through the tri-state buffer when it is "H" or "Lo". A binary-to-ternary conversion circuit can be realized.

Embodiment Hereinafter, a binary-to-ternary conversion circuit according to an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit configuration diagram showing an embodiment of the present invention,
1 and 2 are the same binary input terminals as in FIG. 3, and 12 is a ternary output terminal. 3 is a first inverter, and the input terminal 2 is connected to its input terminal. 4 is an AND gate, the output terminal of the inverter 3 is connected to the first input terminal, and the input terminal 1 is connected to the second input terminal. Reference numeral 5 denotes a tri-state buffer, the input of which is connected to the input terminal 2, and the output enable terminal of which is connected to the output terminal of the AND gate 4. 6 is the second inverter, and its input terminal has A
The output terminal of ND gate 4 is connected. 7 is a voltage source that generates a three-value "M° small output. 8 is an analog switch, and the inverter 6 is connected to the switching terminal of the switch.
output terminal is connected. 12 is a three-value output terminal, and the output terminal of the tri-state buffer 5 and the output terminal of the analog switch 8 are connected.

The operation of the binary-to-ternary conversion circuit configured as described above will be explained below with reference to FIG.

First, input signal D0. of input terminal 1.2. When D is "L" and 'L' respectively, the output of the inverter 3 becomes "Ho", but since Do is "Lo", the output of the AND gate 4 becomes L°. Therefore, the output enable terminal of the tri-state buffer 5 becomes "Lo," and the tri-state buffer 5 becomes the input terminal 2.
input signal. Output. Further, since the output of the inverter 6 becomes °H°, the analog switch 8 is turned off. Therefore, from the output terminal 12, the analog switch 8
is off, the output signal of tristate buffer 5 is output. In other words, "Lo" is output.

Next, input signal D0. of input terminal 1.2. When D is "H" and 'L', respectively, the output signal of the inverter 3 becomes °H, and the output of the AND gate 4 becomes °■1°. Since the output signal of the AND gate 4 becomes "Ho", the output of the tri-state buffer 5 becomes disabled.
The output becomes open. The output of inverter 6 is AN
Since the output signal of the D gate 4 is "Ho", it becomes 7L, the analog switch 8 is turned on, and the M level output signal of the voltage source 7 is output from the output terminal 12. Therefore, the input of the input terminal 1.2 is Signal is on., Dl is °H゛,
At “Lo”, “M” is output from the output terminal 12.

Furthermore, the input signal D0' of the input terminal 1 is "Lo".

When the input signal D1 of the input terminal 2 is "H", the output of the inverter 3 becomes "L", and the AND gate 4 becomes "Lo".
The tri-state buffer 5 becomes output enabled, and the input signal RI of the input terminal 2 is outputted. AN
Since the output signal of the D gate 4 is L, the output of the inverter 6 is 1°, and the analog switch 8 is turned off. As a result, the signal D2 at the second input terminal is output as is from the output terminal 12. Therefore, input terminal 1゜2
When the input signal is “Lo” or “H”, the output terminal 12
``Ho'' will be output from .

Next, input signal D0. of input terminal 1.2. D, respectively °
H゛, When “Ho”, the output of inverter 3 is “Lo”
Then, the AND gate 4 becomes “Lo”. The tri-state buffer 5 becomes output enabled, and the input terminal 20 becomes “Lo”.
Input signal D1 is output. Since the output signal of the AND gate 4 is low, the output of the inverter 6 is high, and the analog switch 8 is turned off. As a result, the signal D2 at the second input terminal is output as is from the output terminal 12. Therefore, the input signal of input terminal 1.2 is L',
When it is 'H', the output terminal 12 outputs 'H'.

From the above operations, the relationship between the level of the signal input to the input terminal 1.2 and the level of the output signal output from the output terminal 12 can be summarized as shown in Table 2. As is clear from Tables 1 and 2, in the input/output characteristics of the binary -3 (fi conversion circuit), the input signal D0.D, is °H", '
The level of the output signal when H° is different, but it should be defined that Do-“H”, D, = 'H' is prohibited at the input signal level, or 'If' level is output. In addition, if the second input signal is H°, the 3(! output is always “Ho”), making it easy to handle binary input signals.

Table 2 Next, Figure 2 shows an example of a configuration of voltage [7]. In order to create an intermediate potential, resistors with the same resistance value are connected in series to the power supply terminals 13 and 14, and the buffer 15 is connected from the connection point. The signal is output from the output terminal 16 via the output terminal 16.

In this way, the H, “Lo” level output and “Mo”
By switching the level output depending on the level of the input terminal l, a binary-to-ternary conversion circuit can be realized with a very simple circuit configuration.

Furthermore, since the "Mo" level output is output using an analog switch, even if there are a plurality of binary-to-ternary conversion circuits, only one circuit is required to generate the "M" level.

Furthermore, since no resistor is connected to the output terminal, there is almost no need to consider impedance matching at the input/output terminals, and since analog switches and tri-state buffers are used, it can be easily realized with a CMOS circuit.

In this embodiment, the polarity of the enable signal for the analog switch and tri-state buffer is treated as negative, but a positive polarity may also be used. In that case, if an inverter is inserted so that the polarities match, Good, also AN
It is also possible to replace the D gate with a NAND gate and match the polarity with an inverter.

Effects of the Invention As described above, the present invention includes an AND gate to which a first binary signal is supplied to the first input terminal, and a first inverter to which the second binary signal is supplied to the input terminal. , the output of the first inverter is supplied to a second input terminal of the AND gate, the output terminal of the AND gate is connected to an enable terminal, and the second binary signal is supplied to an input terminal. a second inverter to which the output terminal of the AND gate is connected to the input terminal; a voltage source that generates a potential at the midpoint of the ternary signal; and an output terminal of the second inverter to which the output terminal is connected. By connecting an analog switch connected to the switch switching terminal and having the output terminal of the voltage source connected to the input terminal, and the output terminal of the tri-state buffer and the output terminal of the analog switch, and outputting from the connection point, A binary-to-ternary conversion circuit can be easily configured, and a single "M" level generation circuit can supply M'' levels to a plurality of binary-to-ternary conversion circuits.

[Brief explanation of the drawing]

FIG. 1 is a circuit configuration diagram of a binary-to-ternary conversion circuit according to an embodiment of the present invention, FIG. 2 is a circuit diagram of a voltage source that generates the °M level, and FIG. 3 is a conventional binary-to-ternary conversion circuit. 3 is a circuit configuration diagram of a 31M conversion circuit. FIG. 5... Tri-state buffer, 7... Old voltage source, 8... Analog switch. Name of agent: Patent attorney Toshio Nakao (1 person)

Claims (1)

[Claims] an AND gate to which a first binary signal is supplied to a first input terminal; a first inverter to which a second binary signal is supplied to an input terminal; a tristate buffer supplied to a second input terminal of the AND gate, an output terminal of the AND gate connected to an enable terminal, and an input terminal of which the second binary signal is supplied; a second inverter whose output terminal is connected to the input terminal; a voltage source that generates a potential at the midpoint of the ternary signal; an output terminal of the second inverter that is connected to the switch switching terminal and whose input terminal receives the voltage An analog switch to which an output terminal of the source is connected, an output terminal of the tri-state buffer, and an output terminal of the analog switch are connected, and an output is generated from the connection point. .