JPS63299518A - 2-value to 3-value conversion circuit - Google Patents

Abstract

PURPOSE:To constitute a binary/ternary converting circuit without connecting a resistance to an output terminal by outputting a 2nd binary input signal from a tristate buffer via the L and H outputs of said converting circuit and outputting the output of a voltage source generating the potential of an intermediate point through an analog switch via the M output. CONSTITUTION:An inverter 3 which receives a 1st binary signal D0 at its input terminal is provided together with a tristate buffer 4 where 1st and 2nd binary signals D0 and D1 are supplied to an enable terminal and an input terminal respectively, a voltage source 5 which produces the potential of an intermediate point of a ternary signal, and an analog switch 6 which functions to connect the output signal to an input terminal and the output terminal of the inverter 3 to a switch changeover terminal respectively. Then the output terminal of the buffer 4 is connected to the output terminal of the switch 6 and the output is outputted through this joint. Thus a binary/ternary converting circuit is easily obtained and the 'M' levels of plural binary/ternary converting circuits can be supplied by a single 'M' level generating circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention is applicable to binary-value signals used for communication in integrated circuits (ICs), etc.
This relates to a three-value conversion circuit.

2. Description of the Related Art In recent years, ternary signals, which are more efficient than binary signals, have come to be used for communication between ICs. By using ternary signals, the number of wires between ICs can be reduced.

Since processing is performed in binary within the IC, binary-to-ternary conversion must be performed when outputting the processing results.

FIG. 3 is a circuit diagram showing a conventional binary-to-ternary conversion circuit, in which 1 is an input terminal to which the first binary signal (Do) is input, and 2 is the input terminal for the second binary signal (D , ) are input terminals. 3 is an inverter, and input terminal 1 is used as an input.
is connected. 4 is a NOR gate, the first input terminal 401 of the NOR gate 4 is connected to the input terminal 1, and the second input terminal 402 is connected to the input terminal 2. 5 is a NAND gate, a first input terminal 501 of the NAND gate 5 is connected to the output terminal of the inverter 3, and an input terminal 502 is connected to the input terminal 2. 6 is a P-channel FET, the gate electrode of which is connected to the output terminal of the NAND gate 5', 7 is an N-channel PI! ? , and the gate electrode is NOR
The output terminal of gate 4 is connected. P channel F
The source terminal of ET6 and the source terminal of N channel are the first
power supply terminal 8 (V, .) and second power supply terminal 9 (vss)
are connected to each. The drain of P-channel FET6 and the drain of N-channel FET7 are connected,
A double FET in which a resistor 10.11 with the same resistance value is connected between the source and drain of each FET.
Connection points 6 and 7 and output terminal 12 are connected, and output terminal 1
A 2- to 3-value signal is output.

The operation of the binary-to-ternary conversion circuit configured as described above will be explained below.

First, when the input signals R, D, of the input terminals 1 and 2 are "L" and 'L', respectively, the output signal of the inverter 3 is
becomes H°, and the input signal of NAND gate 5 becomes 'H°,
“Lo”, so the output signal is °L°.Here, “
Ho is vo at the same level as the first power supply terminal 8. “Lo
has the same level vss as the second power supply terminal 9,
As a result, P channel FE 76 is turned off. Since the input signal of the NOR gate 4 is "Lo, "Lo, the output signal becomes °H°, the N-channel FET 7 is turned on, and the output signal outputted to the output terminal 12 becomes °L°. Therefore, the input signal D0 ．． D.

When each is “Lo,” the output signal of the output terminal 12 is “
It becomes Lo.

Next, input terminal 1 human power signal D0 is °H゛, input terminal 2
When the human input signal D1 is “Lo”, the NAND gate 5
Since the output signal of is high, the P-channel FET 6 is off. The input signal of NOR gate 4 is °H°, “L
o, so the output signal becomes °L° and the N-channel FET 7 is also turned off. Therefore, since both FETs 6 and 7 are turned off, the level of the signal output from the output terminal 12 is determined by the resistor 10.11 connected between the power supply terminals 8 and 9, and since the resistance values of the resistors 10 and 11 are the same, The output signal level is V. , /2. That is, it outputs the "M' level, which is the intermediate potential level.

Furthermore, the input signal D0 of the input terminal l is L°.

When the input signal D1 of input terminal 2 is “Ho”, NAN
Since the input signals of the D gates 5 each become "H", the output signals become "Lo" level, and the P channel FET 6 turns on.The human input signals of the NOR gates 4 each become "L".
, becomes 'H', so the output signal becomes L',
The N-channel FET 7 is turned off, and the output signal output to the output terminal 12 becomes "H". Therefore, when the input signal D0°Dl is 'L° and "H", the output signal of the output terminal 12 becomes "Ho".

Next, input signal D0 of input terminal l is “Ho, input terminal 2
When the input signal RI is “Ho”, the NAND gate 5
The input signal is °L°, “Ho”, and the output signal is “H”.
o, so the P-channel FET 6 is turned off. N
Since the input signals of the OR gate 4 each become "H", the output signal becomes °L°, the N-channel FET 7 is also turned off, and the output signal is determined by the resistor 10.11 and becomes "M".

From the following operation, input terminal 1. The relationship between the level of the signal input to the output terminal 2 and the level of the output signal output from the output terminal 12 can be summarized as shown in Table 1.

Table 1 Problems to be Solved by the Invention However, in the above configuration, since a resistor is connected to the output terminal, if there are multiple binary-to-ternary conversion circuits, it is difficult to determine the "M° ratio output". However, a resistor is required for each output terminal.Furthermore, there is a problem in that the input impedance on the side receiving the ternary output must be larger than the resistor that determines the ternary output.

In view of the above-mentioned problems, the present invention provides a binary-to-ternary conversion circuit that can output "M level" without connecting a resistor to the output terminal of the binary-to-ternary conversion circuit.

Means for Solving the Problems In order to solve the above problems, the binary-to-ternary conversion circuit of the present invention includes: an inverter to which a first binary signal is supplied to an input terminal; a tri-state buffer with a signal supplied to an enable terminal and a second binary signal supplied to an input terminal; a voltage source generating a potential at the midpoint of the ternary signal; and an output signal of the voltage source supplied to the input terminal. an analog switch connected to the inverter and an output terminal of the inverter connected to a switch switching terminal; an output terminal of the tri-state buffer and an output terminal of the analog switch;
It is characterized in that an output is generated from the connection point.

Operation According to the above-described configuration, the "Lo" and "H" outputs of the binary-to-ternary conversion circuit output the second binary input signal D1 from the tri-state buffer, and the °M output is the potential at the midpoint. Since the output of the voltage source that generates is outputted via an analog switch, a binary-to-ternary conversion circuit can be constructed without connecting a resistor to the output terminal to determine the °M ° output. In addition, the conversion from binary to ternary value is also simple because the second binary input signal D1 is outputted only through the tri-state buffer when "I('," is "L"). A binary-to-ternary conversion circuit can be realized.

Embodiment Hereinafter, a 24M-3 value conversion circuit according to an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit configuration diagram showing an embodiment of the present invention,
1 and 2 are the same binary input terminals as in FIG. 3, and 12 is a ternary output terminal. 3 is an inverter, and an input terminal l is connected to the input.

Reference numeral 4 designates a tri-state buffer, the input of which is connected to input terminal 2, and the output enable terminal of which is connected to input terminal 1. 5 is a voltage source that generates a 3-value "M" output. 6 is an analog switch, and the output terminal of the inverter 3 is connected to the switching terminal of the switch. 12 is a 3-value output terminal, which is a tri-level output terminal. The output terminal of the state buffer 4 and the output terminal of the analog switch 6 are connected.

The operation of the binary-to-ternary conversion circuit configured as described above will be explained below with reference to FIG.

First, when the input signals R, D, of input terminals 1 and 2 are 'L' and 'L', respectively, the output of inverter 3 is °
H°, the analog switch 6 is not connected, and the tri-state buffer 4 has a signal D0 at the input terminal l that is 'L'.
°, the output is enabled, and the human input signal at the input terminal 2 is output as is. Therefore, since the analog switch 6 is off, the output signal of the tri-state buffer 4 is output from the output terminal 12. In other words, "L" is output.

Next, when the input signals R, D, of input terminals 1 and 2 are °H' and 'L', respectively, the tri-state buffer 4
Since the signal D0 at the input terminal l becomes H', the output is disabled and the output becomes open. Since the input signal D0 of the input terminal 1 is "Ho", the output of the inverter 3 becomes L, and the analog switch 6 is turned on, so that the M level output signal of the voltage source 5 is output from the output terminal 12. Therefore, the input signal D0 at input terminal 1.2
．． When D is "Ho" or "Lo", "M" is output from the output terminal 12.

Furthermore, the input signal D0 of the input terminal 1 is "Lo".

Input signal D1 of input terminal 2 is °! 1, the output of the inverter 3 becomes "Ho" and the analog switch is turned off. Since the input signal D0 of the input terminal 1 is "Lo", the tri-state buffer 4 becomes output enabled, and the input signal D2 of the input terminal 2 becomes "Lo". is output as is from the output terminal 12. Therefore, the input signal of input terminal 1.2 is "Lo".

■(°) “Ho” is output from the output terminal 12.

Next, input signals D0. of input terminals 1 and 2. D1 is “
Since the input signal D0 is "11", the output of the tri-state buffer 4 is disabled and the analog switch 6 is turned on. As a result, an M level output signal of voltage source 5 is output from output terminal 12. Therefore, the input signals at input terminals 1 and 2. ,Dl
is H°.

When the temperature is °H°, "M" is output from the output terminal 12.

From the above operations, the relationship between the level of the signal input to the input terminal 1.2 and the level of the output (No. 3) output from the output terminal 12 can be summarized as shown in Table 2. As is clear from Table 2, there is no change in the input/output characteristics of the binary-to-ternary conversion circuit.

(Margins below) Table 2 and Figure 2 show an example of the configuration of the voltage source 5. In order to create an intermediate potential, resistors with the same resistance value are connected in series to the power supply terminals 8 and 9. The signal is output from the connection point via the buffer 13 and from the output terminal 14.

In this way, by switching between the "■1", "L" level output and the "M" level output according to the level of input terminal 1, binary -3 can be achieved with a very simple circuit configuration.
A value conversion circuit can be realized.

Further, since the output at the °M level is output using an analog switch, even if there are a plurality of binary-to-ternary conversion circuits, only one circuit is required to generate the "M" level.

Furthermore, since no resistor is connected to the output terminal, there is almost no need to consider impedance matching at the input and output terminals. Furthermore, since analog switches and tri-state buffers are used, it can be easily realized with a CMO3 circuit.

In this embodiment, the polarity of the enable signal for the analog switch and tri-state buffer is treated as negative, but a positive polarity may also be used. In that case, if an inverter is inserted so that the polarities match, good.

Effects of the Invention As described above, the present invention provides an inverter in which a first binary signal is supplied to an input terminal, and an inverter in which the first binary signal is supplied to an enable terminal and a second binary signal is supplied to an input terminal. a tri-state buffer, a voltage source that generates a potential at the midpoint of a three-value signal, and an analog switch in which the output signal of the voltage source is connected to an input terminal and the output terminal of the inverter is connected to a switch switching terminal. By connecting the output terminal of the tri-state buffer and the output terminal of the analog switch, and outputting from the connection point,
A binary-to-three-value conversion circuit can be easily configured, and one 'M'
Multiple 2-value to 3-value conversion circuits ゛M° in the level generation circuit
level can be supplied.

[Brief explanation of the drawing]

FIG. 1 is a circuit configuration diagram of a binary-to-ternary conversion circuit according to an embodiment of the present invention, FIG. 2 is a circuit configuration diagram of a voltage source that generates the "M" level, and FIG. 3 is a circuit diagram of a conventional binary-to-ternary conversion circuit. It is a circuit configuration diagram of a three-value conversion circuit. 4... Tri-state buffer, 5...
・Voltage source, 6...Analog switch.

Claims (1)

[Claims] an inverter whose input terminal is supplied with a first binary signal;
a tri-state buffer in which the first binary signal is supplied to an enable terminal and the second binary signal is supplied to an input terminal; a voltage source that generates a potential at an intermediate point of the ternary signal; An analog switch in which an output signal is connected to an input terminal and an output terminal of the inverter is connected to a switch switching terminal, an output terminal of the tri-state buffer and an output terminal of the analog switch are connected, and an output is generated from the connection point. A binary-to-ternary conversion circuit characterized by: