JPS63299542A - Digital phase control circuit - Google Patents

Abstract

PURPOSE:To prevent the loop gain of a complete secondary system from being set under a plus state and also to improve the step answer characteristics, by setting the damping coefficient rho of the system at the valve much larger than 1 in a digital phase control circuit of the system. CONSTITUTION:A multi-level quantizing phase comparator 11 is provided together with K1-K3 counters 12-14, a rate multiplier circuit 15, a 1-pulse adding/deleting circuit 18, an R divider 19, a high-speed clock oscillator 20 which applies the clock pulses to the comparator 11 and the circuit 18, OR gates 23, 26, 17 and 21, and gates 16 and 22. Then the damping coefficient rhoof a system is set as rho>>1 so that the loop gain of the system can be prevented from being set under a plus state in terms of a natural frequency, and the step answer characteristic is improved.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a digital phase control loop circuit used in a smoothing circuit on the reception side of a stuff synchronizer.

(Prior Art) Conventionally, in this type of phase control circuit, in order to optimize the transient response speed, it has been common to set the damping coefficient ρ of the system to ρ=1.

(Problems to be Solved by the Invention) In the conventional system described above, when a fully quadratic digital phase control circuit is used, the natural frequency ω. The disadvantage is that there is a point where the loop gain of the system becomes positive. Furthermore, it has been found that when a fully quadratic digital phase control circuit is used, the transient response speed is not necessarily optimized even when the braking coefficient ρ=1.

The present invention solves the above problems and reduces the natural frequency ω.

An object of the present invention is to provide a digital phase control circuit capable of suppressing the loop gain of the system from becoming positive at the point , and improving step response characteristics.

(Means for Solving the Problems) The present invention is a completely quadratic digital phase control circuit in which the damping coefficient ρ of the system is set to be ρ>>1.

(Example) Next, one embodiment of the present invention will be described with reference to one drawing.

FIG. 1 is a block diagram of a fully quadratic digital phase control circuit according to an embodiment of the present invention, and FIG. 2 is a diagram showing the embodiment of the present invention using a linear loop model. In FIG. 1, the digital phase control circuit of this embodiment includes a multi-level quantization phase comparator 11, K+, Kz, Ks
A clock pulse is given to the counter 12.13° 14, the rate multiplier circuit 15, the 1-pulse addition/removal circuit 18, the R frequency divider 19, the phase comparator 11 and the 1-pulse addition/removal circuit 18. It has a high speed clock oscillator 20, OR gates 23, 26, 17 and 21, and gate 16, 22. 24 and 251d are input signals and output signals of the multilevel quantization phase comparator 110.

Referring to FIG. 2, the forward gain of the loop is:

μ = 1-2 (1+ 3・K4/S) ・Kt
/ It is given by S. Here, 10 to 3·K4/S acts as a loop filter, and the transmission interval is a F(9).

therefore.

μ= (Kl−2)・(F(s))・(Kt/
S) = -F(1)/S. Further, the amount of feedback is β=1.

If we calculate the input/output transfer function here, the negative feedback equation can be considered to be: The denominator of the above equation is a quadratic equation of the following form. That is.

Therefore.

Transforming into

The damping coefficient (damping rate) ρ is.

Therefore, the transfer function of a complete quadratic system is obtained as the transfer function of the quadratic loop. Here, when we calculate the response to the sine wave Jitter VC, we get the sine wave Ji
The response to tter Ic is obtained by setting S=jω. Here, from the multiplication law of complex numbers, IGI(j
ω)・Gz(jω)l=lGs(jω)I・Ic鵞(j
ω)1 G1(jω)・Gz(jω)=lGs(jω)
+tGz(jω) is obtained, and therefore, the power gain I)((ω)12 of the transfer function of the quadratic loop system is determined as follows.

Here, the damping coefficient ρ is expressed as the normalized frequency ω/ωnt” variable.
When the frequency response, that is, the amount of attenuation is determined using as a parameter, a response characteristic as shown in FIG. 3 is obtained. As is clear from FIG. 3, as the damping coefficient ρ becomes smaller, the loop gain becomes positive at the natural frequency ωn.

Next, the transient response in the completely secondary digital phase control circuit is determined. Now, if the overall transformation function of the system is expressed by h(t) and the input signal eX(t), then its output waveform y(
t) is.

It is expressed as a convolution: y(t)=H(t)X(t).

This can be done by applying Laplace transform.

Y(8)=H(8)・X(8) If we apply the inverse transformation again, we get

It is given by y(t)=f−'(H(s)·X(8)).

Here, we will find the response of the system when a unit step function is input. In this case, the input signal is.

x(t)=u(t) or X(8)=-! − is.

Therefore Here is the discriminant equation.

D=4(ωn)ゝ(ρ2-1) It is.

Now, when the discriminant equation is D(1, that is, when ρ is 1, then 5l=-ρωn+jωnV1-ρ2 S2=-ρωn+jωnf+1) Here, we obtain Ko=1.If we perform the mania transformation here.

Z −' Y (B) = 7 (t) = Ko 1 Kl
e slt+ 1(2e "t+2ρ stone-p" 5in
(v'1-p2 ωnt)) Also, the 1st discriminative sword equation is D>1
That is, if ρ〉1, Vi, ! −' Y (S) = 7 (t) =Ko+K
le, “t+K2e”, then 1 discriminator sword type is D=1
That is, when ρ=1, the value is calculated.

Here, we obtain =ωn K2 = -1 for Ko=1. If we perform the inverse transformation here, J, -' Y(3) = 7(t) = Ko+ K1・
te-'nt+2.6-"Itt=1+e""
The 0nt (ωnt-1) step response characteristic was calculated using the braking coefficient ρ as a parameter, and the results are shown in FIGS. 4 to 11.

As is clear from this, it can be seen that the larger the braking characteristic ρ becomes, the more the response characteristic is improved.

(Effects of the Invention) As described above, the present invention sets the damping coefficient ρ of the system to ρ>>1 in a fully quadratic digital phase control circuit, thereby reducing the natural frequency ω.

This has the effect of suppressing the loop gain of the system from becoming positive at the point , and at the same time improving the response characteristics of the step response as shown in FIG.

[Brief explanation of drawings]

Fig. 1 is a block diagram of a fully quadratic digital phase control circuit according to an embodiment of the present invention, Fig. 2 is a diagram showing an embodiment of the present invention as a linear model of the system, and Fig. 3 is a frequency response of the system. 4 to 11 are diagrams showing the step response of the system to various damping coefficients. 11...Multi-level quantization phase comparator. 12...K! Counter, 13...K: Counter, 14...K3 counter, 15... Rate multiplier circuit. 16.22... Gate. 17.21, 23.26...OR gate
. 18...L pulse addition/removal circuit, 19...R frequency divider, 20...high speed clock generator, 24...input signal, 25...output signal.

Claims (1)

[Claims] 1. A completely secondary digital phase control circuit, characterized in that a damping coefficient (damping rate) ρ of the system is set to a value much larger than 1.