JPS63299544A - Frame synchronizing circuit - Google Patents

Abstract

PURPOSE:To execute frame synchronization at an extremely high speed in various communication systems in a simple circuit constitution, by setting a shift control part into a frame synchronizing circuit. CONSTITUTION:A shift control part 13 is set into a conventional frame synchronizing circuit to receive a shift signal 10B from a decoder 6 via a buffer 9 and changes the preset valve of a frame counter 1 by an amount equal to the shift bits. Thus the part 13 changes the preset value by an amount equal to the number of shift bits of the counter 1 based on the signal 10B and obtain a synchronizing bit pattern. As a result, the synchronizm resetting time is shortened.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a frame synchronization circuit that is applied to a communication system having a frame structure for voice or data transmission, etc., and particularly relates to a frame synchronization circuit that can shorten synchronization time. .

[Prior Art] A conventional circuit of this type will be explained based on FIG. Fourth
The circuit shown in the figure shows the 1-bit shift frame synchronization method described in "Digital Communication Technology" (written by Kimio Tanaka, published by Tokai University Press), which shifts the bit information in the frame to 1 bit. This is done by shifting and synchronizing each other. In the figure, (1) is a frame counter that counts bit information in one frame using the clock signal (2) coming from the other station, and (3) is a frame counter (1).
A multi-frame counter (4) counts the number of frames based on the signal from the frame counter (1), stores the bit information signal from the frame counter (1), detects the beginning of the frame, and receives the data signal (5), and processes both of them. Decoder (
6), the decoder (6) determines whether or not both signals are synchronized, and if they are synchronized, transmits a frame pulse signal (7) and a multi-frame pulse signal (8). , if the data latched in the latch circuit (4) and the true first bit of the frame are compared and the two are not synchronized, a 1-bit shift signal (IOA) is sent to shift the frame counter (1) by 1 bit. It is made to be. (9) is this shift signal (
IOA) and multi-frame counter (
This buffer controls the timing at which the gate is opened by the signal (11) from 3) and outputs the shift signal (10) to the frame counter (1) as the shift signal (10B).

Next, the operation will be specifically explained with reference to FIGS. 5 and 6. FIG. 5 shows a 12-multiframe structure of a T1 interface, which is an example of communication having a frame structure in serial transmission. The TI Zein interface has an FT/FS bit at the beginning of the frame for frame synchronization and multi-frame synchronization, and also has 24 slots of 8 bits per channel following this bit, and 193 bits per frame. Twelve frames constitute one multiframe.

However, first, the latch circuit (4) receives the data signal (5).
A frame counter (1) receives a clock signal (2) synchronized with a data signal (5). Frame counter (1
) assumes that a certain point is the beginning of a frame and outputs a signal every 193 bits based on that point. When the latch circuit (4) receives this signal, it latches and stores the received data every 193 bits. The latch circuit (4) sends 12 bits, which are the first bits of each assumed multi-frame, to the decoder (6) in parallel, and if the above data is correct FT/FS bits synchronized with the frame, the decoder (6) sends a frame pulse signal. (7), the multi-frame pulse signal (8) is transmitted, but if it is incorrect, a 1-bit shift signal (10^) is transmitted and the 1-bit shift signal (10^) is sent through the buffer (9).
It is sent to the frame counter (1) as a bit shift signal (IOB). At this time buffer (9)
The gate is opened every multiframe by the signal (11) from the multiframe counter (3), and the shift timing for the frame counter (1) is controlled. Therefore, the frame counter (1) is the buffer (9)
Based on the 1-bit shift signal (10B) from the decoder (6), the frame pulse signal (7) and multi-frame pulse signal (8) are transmitted in synchronization with the frame and data, one bit at a time from the assumed leading bit. It will be repeated until

By doing this, the frame synchronization method can be adopted with less hardware, which is economical.

[Problems to be Solved by the Invention] However, assuming that the communication system is, for example, a private branch exchange (PBX) and a multimedia multiplexer (MIX), it is difficult to synchronize data coming from the PBX on the MIX side. If a communication failure occurs and data is disrupted, the PBX performs a so-called flywheel operation in which it attempts to transmit data at the same timing by extrapolating a virtual frame pulse signal. However, even after the data has been recovered, there is a high probability that the beginning of the frame will be at the same position. The synchronization state is recovered only after all the bit information in one frame is searched, and it takes time to recover.

The present invention has been made to solve the above problems,
The purpose is to further shorten the frame synchronization establishment time while effectively utilizing the advantages of conventional hardware.
Ru.

[Means for Solving the Problems] The present invention incorporates a shift control section into a conventional frame synchronization circuit, which receives a shift signal from a decoder via a buffer and changes a preset value of a frame counter by an amount equivalent to the shift. It is composed of.

[Operations] According to the present invention, the shift control unit changes the number of shift bits of the frame counter based on the shift signal from the decoder, and performs control to obtain a synchronized bit pattern, thereby shortening the synchronization recovery time. be able to.

[Embodiment] Hereinafter, based on FIGS. 1 to 3, the same or equivalent parts as those in the conventional art will be given the same reference numerals, and the explanation thereof will be omitted, and the features of the present invention will be mainly explained.

In Figure 1, (13) detects the number of bits that the frame is shifted from the synchronized state based on the shift signal (IOB) from the buffer (9), and transmits this number of bits as a shift bit signal (14). This is a shift control unit that controls to shift the beginning of the assumed frame detected by the frame counter (1) and to latch the beginning bit of the frame from there.

A specific example of the shift control section (13) is shown in FIG. 2, and according to the figure, the shift control section (13) receives the shift signal (10B
) and an up counter (16) that is reset by receiving a signal from the position register (15).
) and a down counter (17), and these up counter (16) and down counter (17) toggle a signal based on the next shift signal (IOB) transmitted by the buffer (9). 18) and transmit the respective signals together with the position register (15) to the selector (19), the selector (19) sequentially switches these signals as shown in FIG. , the left and right bits are sequentially searched outward from the beginning of the frame as 1 bit, 2 bits, 3 bits, etc., the required number of shift bits is detected, and the selector (1
9) to the frame counter (1) shift bit signal (
20), the beginning of the assumed frame is shifted at once by the number of shift bits, and the frames are synchronized. Therefore, even though there is the flywheel operation described above, in this embodiment, unlike the conventional method in which synchronization is achieved by shifting the beginning of the frame one bit at a time, the number of shift bits is detected by the shift control section (13). Since the shift bit signal (20) is sent to the frame counter (1) and the beginning of the frame is shifted by that amount to achieve synchronization, the synchronization recovery time can be shortened.

Note that the means for detecting the number of shift bits by the shift control section (13) is not limited to the circuit configuration shown in FIG. Any device that can achieve substantially the same effects as the example is included in the present invention.

Furthermore, the transmission method is not limited to serial transmission;
It can also be applied to parallel transmission.

[Effects of the Invention] According to the present invention, frame synchronization in various communication systems can be performed extremely quickly with an extremely simple circuit configuration in which a shift control section is incorporated into a frame synchronization circuit.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the frame synchronization circuit according to the present invention, FIG. 2 is a diagram corresponding to FIG. 1 showing the shift control section in FIG. 1, and FIG. A diagram showing a search pattern for the first bit of a frame by the control unit, FIG. 4 is a diagram equivalent to FIG. 1 showing a conventional circuit, FIG. 5 is a T1 interface showing an example of human input to the frame synchronization circuit, and FIG. FIG. 3 is a diagram showing a search pattern for the first bit of a frame. In the figure, (1) is a frame counter, (4) is a latch circuit, (6) is a decoder, (IOA), (IO
B) is a shift signal, (13) is a shift control section, (14)
is a shift bit signal, (15) is a position register, (16
) is an up counter, (17) is a down counter, (1
8) is a toggle flip-flop, and (19) is a selector. In each figure, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Claims] A latch circuit that obtains bit information in a frame from a frame counter and stores it; and a latch circuit that obtains the bit information from the latch circuit and a signal to synchronize the bit information and determines whether or not the bit information is a synchronous bit pattern. a decoder that detects the number of bits shifted from the reference value based on the shift signal from the decoder, and detects the number of bits shifted from the reference value based on the shift signal from the decoder, 1. A frame synchronization circuit comprising: a shift control section that shifts a preset value of a counter by the detected value.