JPS63299577A - clamp device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a clamp that clamps the signal to a predetermined value within the digital output range of an A/D converter at a predetermined timing when converting an analog signal to a digital signal. It is related to the device.

BACKGROUND OF THE INVENTION In recent years, clamp devices in digital signal processing units including A/D converters are often configured to compare the digital output of the A/D converter with a set digital value and clamp the signal. . (For example, JP-A-58-1243
(Japanese Patent No. 73) Hereinafter, an example of the above-mentioned conventional clamp device will be described with reference to the drawings.

FIG. 3 shows the basic configuration of a conventional clamp device. In FIG. 3, 2 is an A/D converter, 4 is a clamp signal generation circuit, 7 is a two-signal analog addition circuit, and 8 is a two-signal analog adder.
A D/A converter having the same number of bits as the A/D converter of 9
1 is a digital filter circuit, 1O is a two-signal digital subtraction circuit, 11 is a sample hold circuit, and 12 is a reference level generation circuit for generating a predetermined clamp level.

The operation of the clamp device configured as described above will be explained below.

First, an analog signal 71 input manually from the input terminal 1 is added to an error signal 72 by the adding circuit 7. The adder ratio cuff 3 is input to the A/D converter 2, and the digital signal 2
It is converted to 2. The digital signal 22 is sampled and held by the sample and hold circuit 11 and input to the i4 arithmetic circuit 10.

In the subtraction circuit 10, the sample and hold circuit output 111 is subtracted from the reference level signal 121, and the output 101 passes through the filter circuit 9 and the D/A converter 8 and becomes an error signal.

Through the above control loop, the clamp level of the output digital signal 22 converges to the predetermined reference level 121.

Problems to be Solved by the Invention However, with the above configuration, the circuit configuration is complicated, and the signal level at the time of clamping is extracted in the form of a digital signal and compared with a predetermined reference digital signal. However, there is a problem in that it is impossible in principle to reduce the fluctuation of the clamp level to one quantization level or less.

For example, if a television signal as shown in FIG. 4 (al) is input from input terminal 1 and the pedestal level is clamped to a constant digital value,
The input signal 73 of the D converter has the waveform shown in FIG. 4 (bl, tel), and the pedestal level of the analog television signal fluctuates by one quantization level ΔV as shown in FIG. 4 (C1).

In view of the above-mentioned problems, the present invention provides a clamp device with a simple circuit configuration and small clamp level fluctuations.

Means for Solving the Problems In order to solve the above problems, the clamping device of the present invention includes an A/D converter and a digital output signal of the A/D converter that outputs the most significant bit at a predetermined timing. A configuration that includes a latch circuit that latches, an integrator that integrates the output of the latch circuit, and an adder circuit that adds the output of the integrator and the analog signal that is input to the clamp device at a stage before the A/D converter. It is.

Operation The present invention has a simple circuit configuration due to the above configuration,
Furthermore, since the digital output signal during clamping is clamped at the transition point of the most significant bit signal of the A/D converter output, the clamp level hardly changes.

EXAMPLE Hereinafter, a clamp device according to an example of the present invention will be described with reference to the drawings.

FIG. 1 shows the basic configuration of a clamp device in an embodiment of the present invention. In FIG. 1, 2 is an A/D converter, 3 is a latch circuit, 5 is an integrator, and 7 is an adder circuit that adds the input analog signal and the output of the integrator 4.

The operation of the clamp device configured as described above will be explained using FIG. 1. An analog signal 71 input from the input terminal 1 is added to an error signal 72 by the adder circuit 7. The adding circuit cuff 3 is connected to an A/D converter 2.
and is converted into a digital signal 22. Only the most significant bit signal 31 of the digital signal 22 is latched by the latch circuit 3 at a predetermined timing determined by the clamp position signal 32. The output 33 of the latch circuit 3 indicates whether the A/D converter input signal 73 is greater or less than a predetermined clamp reference level during clamping. The output 33 of the latch circuit 3 is input to the integrator 5, and the integrated product output cuff 2 becomes an error signal to the adder circuit 7.

Through the above control loop, the clamp level of the output digital signal 22 converges to the level at the turn of the most significant bit signal output from the A/D converter.

For example, FIG. 2 shows the waveforms of various parts when a television signal as shown in FIG. 2 (3) is input from the input terminal l and the pedestal level is clamped. Since the pedestal level exists near the center of the amplitude of the television signal waveform, it is suitable for use with the present clamping device. The integrator output signal 72 is shown in FIG. 2(b), and the A/D converter input signal 73 is shown in tel.
, indicating a clamped analog signal.

As described above, according to this embodiment, the pedestal level of the television signal can be clamped at the transition of the most significant bit signal of the output digital signal with a simple circuit configuration, and the pedestal level can be made to have almost no fluctuation. Also,
Since only the topmost via of the A/D converter output is used for the feedback signal for clamping, the circuit configuration is simple.

Effects of the Invention As described above, the present invention provides an A/D converter, a latch circuit that latches the most significant bit output of the A/D converter at a predetermined timing, an integrator that integrates the output, and an integrator. By providing an adder circuit that adds the output and input analog signals at a stage before the A/D converter, clamping can be performed with almost no variation in the clamp level.

[Brief explanation of the drawing]

Figure 1 is a basic configuration diagram of a clamp device according to an embodiment of the present invention, Figure 2 is a waveform diagram of each part in Figure 1, Figure 3 is a basic configuration diagram of a conventional clamp circuit, and Figure 4 is a waveform diagram of each part. It is a diagram. 2...A/D converter, 3...Latch circuit, 4...Clamp signal generation circuit, 5...
...Integrator, 7... Addition circuit, 72...
・Error signal. Name of agent: Patent attorney Toshio Nakao (1 person) Figure 1 Figure 2

Claims (1)

[Claims] an A/D converter, a latch circuit that latches the most significant bit of the digital output signal of the A/D converter at a predetermined timing, an integrator that integrates the output of the latch circuit, and an output of the integrator. and an analog signal input to the clamp device at a stage before the A/D converter.