JPS63300541A - Semiconductor device package - Google Patents

Semiconductor device package

Info

Publication number
JPS63300541A
JPS63300541A JP62137244A JP13724487A JPS63300541A JP S63300541 A JPS63300541 A JP S63300541A JP 62137244 A JP62137244 A JP 62137244A JP 13724487 A JP13724487 A JP 13724487A JP S63300541 A JPS63300541 A JP S63300541A
Authority
JP
Japan
Prior art keywords
leads
external
insulator
package
peripheral edge
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62137244A
Other languages
Japanese (ja)
Inventor
Hiroshi Koyanagi
博 小柳
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP62137244A priority Critical patent/JPS63300541A/en
Publication of JPS63300541A publication Critical patent/JPS63300541A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W42/00—Arrangements for protection of devices
    • H10W42/121—Arrangements for protection of devices protecting against mechanical damage
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/884—Die-attach connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To prevent external leads from damaging by providing a protecting insulator for surrounding the leads at the peripheral edge of a package. CONSTITUTION:An insulating substrate 5 is formed with a protecting insulator 5A at its peripheral edge. The insulator 5A is so formed as to surround external leads 1. The section 1 protruding from the lead 1 is completely surrounded by the insulator 5A so that an external force is not applied directly. The electrodes of a semiconductor chip 4 are connected by wirings 3 to outgoing leads 6 provided at the substrate 5, and the leads 6 are further connected to the leads 1. Thus, the insulator for surrounding the external leads is provided at the peripheral edge of a package to eliminate the external force directly to the external leads. In this manner, it can prevent the leads from malfunctioning, such as bending or breaking.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、半導体装置のパッケージに関する。[Detailed description of the invention] [Industrial application field] The present invention relates to a package for a semiconductor device.

〔従来の技術〕[Conventional technology]

従来の半導体装置のパッケージは、リードレスタイプは
別として細長い外部リードを絶縁部材のパッケージから
引出して、プリント基板の配線に電気接続をなしている
。In conventional semiconductor device packages, apart from leadless types, elongated external leads are drawn out from the package made of insulating material and electrically connected to wiring on a printed circuit board.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上記のパッケージでは、外部リードが外部に引出されて
いるので、パッケージの取扱いを慎重にしないと、外部
リードに外力が加わ）リーード曲がシ、折れ等の不良が
おきゃすい。In the above package, the external leads are drawn out to the outside, so if the package is not handled carefully, external force will be applied to the external leads, which may cause defects such as bending or bending the leads.

本発明の目的は、前記のように外部リード引出し型の半
導体装置パッケージにおいて、外部リードの損傷を防ぐ
ことのできる構造のパッケージを提供することにある。SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device package of the external lead pull-out type as described above, which has a structure that can prevent damage to the external leads.

〔問題点を解決するための手段〕[Means for solving problems]

本発明は、パッケージの周縁に、外部リードを図む保護
絶縁部を設けるようにしたものである。According to the present invention, a protective insulating portion for forming external leads is provided around the periphery of the package.

〔実施例〕〔Example〕

以下１図面を参照して、本発明の実施例につき説明する
。第１図は、災地利の平面図、第２図はＡＡ’縦断面図
、第３図は底面図である。絶縁基板５は周縁に保護絶縁
部５Ａを設けである。Embodiments of the present invention will be described below with reference to one drawing. Figure 1 is a plan view of the disaster area, Figure 2 is a vertical sectional view along AA', and Figure 3 is a bottom view. The insulating substrate 5 is provided with a protective insulating portion 5A at its periphery.

この保護絶縁部５Ａは外部リード１１ｒ、囲むように形
成されている。外部リード１は絶縁基板５かも突出した
部分１′が、完全に保護絶縁部５Ａによって囲まれ、外
力が直接に加わらないようにしている。なお図において
、半導体チップ４の各電極は、絶縁基板５に設は友引出
し線６にワイヤ３によって連結され、さらに引出し線６
が外部リード１と連結されている。２は封止キャップで
ある。This protective insulating portion 5A is formed to surround the external lead 11r. A portion 1' of the external lead 1 that protrudes from the insulating substrate 5 is completely surrounded by a protective insulating portion 5A to prevent direct application of external force. In the figure, each electrode of the semiconductor chip 4 is connected to a lead wire 6 provided on an insulating substrate 5 by a wire 3, and further connected to a lead wire 6.
is connected to external lead 1. 2 is a sealing cap.

保護絶縁部は、絶縁基板５の周縁全部に連続して設けず
、第４図の底面図に示すように、外部リード１の突出部
分１′の各々を保護するように、保護絶縁部５Ｂを個別
的に形成するようにしてもよい。The protective insulating part 5B is not provided continuously along the entire periphery of the insulating substrate 5, but is provided so as to protect each of the protruding parts 1' of the external lead 1, as shown in the bottom view of FIG. They may be formed individually.

（発明の効果〕 以上説明したように、本発明では外部リードを囲む保護
絶縁部をパッケージ周縁に設けることにより、外部リー
ドに直接外力が加わらないようＫしている。これによっ
てリード曲が）、リード折れ等の不良発生を防ぐことが
できる。(Effects of the Invention) As explained above, in the present invention, a protective insulating portion surrounding the external leads is provided at the periphery of the package to prevent direct external force from being applied to the external leads. It is possible to prevent defects such as lead breakage.

【図面の簡単な説明】[Brief explanation of drawings]

第１図〜第３図は、それぞれ実施例の平面図、Ａ−Ａ’
線線断断面図底面図、第４図は別の実施例の底面図であ
る。 １・・・外部リード、　　　２・・・封止キャップ、３
・・・ワイヤ、　　　　　４・・・半導体チップ、５・
・・絶縁基板、　　　５Ａ、５Ｂ・・・保護絶縁部、６
・・・引出し線。 特許出題式　日本電気株式会社 代理人　弁理士　　内　　原　　　　　晋、ハ！、７ｎ
ｔ〜）＼（・“　−′1 to 3 are plan views of the embodiment, A-A'
FIG. 4 is a bottom view of another embodiment. 1... External lead, 2... Sealing cap, 3
...Wire, 4...Semiconductor chip, 5.
...Insulating substrate, 5A, 5B...Protective insulation part, 6
...Leader line. Patent question ceremony Susumu Uchihara, patent attorney representing NEC Corporation, ha! , 7n
t〜)＼(・“ −′

Claims (1)

【特許請求の範囲】[Claims] 半導体素子の封止絶縁部材から引出された外部リードを
有するパッケージの周縁に、前記外部リードを囲む保護
絶縁部を設けたことを特徴とする半導体装置のパッケー
ジ。1. A package for a semiconductor device, characterized in that a protective insulating part surrounding the external lead is provided at the periphery of the package having an external lead drawn out from a sealing insulating member of a semiconductor element.
JP62137244A 1987-05-29 1987-05-29 Semiconductor device package Pending JPS63300541A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62137244A JPS63300541A (en) 1987-05-29 1987-05-29 Semiconductor device package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62137244A JPS63300541A (en) 1987-05-29 1987-05-29 Semiconductor device package

Publications (1)

Publication Number Publication Date
JPS63300541A true JPS63300541A (en) 1988-12-07

Family

ID=15194138

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62137244A Pending JPS63300541A (en) 1987-05-29 1987-05-29 Semiconductor device package

Country Status (1)

Country Link
JP (1) JPS63300541A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5726493A (en) * 1994-06-13 1998-03-10 Fujitsu Limited Semiconductor device and semiconductor device unit having ball-grid-array type package structure

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5726493A (en) * 1994-06-13 1998-03-10 Fujitsu Limited Semiconductor device and semiconductor device unit having ball-grid-array type package structure

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