JPS63300560A - Insulated-gate bipolar transistor - Google Patents

Abstract

PURPOSE:To reduce the resistance of an offset structure by composing the channel region of a field-effect transistor together with an emitter region of an offset gate forming region as the structure. CONSTITUTION:A second conductivity type emitter diffused region 2, a base diffused region 3 and a high concentration back gate region 11 are formed on the surface of a substrate 1. A second conductivity type collector diffused region 4 is formed in the region 3. A polysilicon gate electrode 5 is formed through a thin gate insulating film on an offset gate forming region 9 adjacent to the region 2, and an interlayer insulating film 6 is interposed between the electrode 5 and an emitter electrode 7. Accordingly, the channel of a field-effect transistor which contains the electrode 5 can be formed of an offset gate type, can reduce a resistance component which was impossible in a double diffusion, thereby preventing a latchup phenomenon from occurring.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an insulated gate bipolar transistor.

[Prior Art] Conventionally, this type of insulated gate bipolar transistor includes a vertical insulated gate bipolar transistor as shown in FIG. 3 and a horizontal insulated gate bipolar transistor as shown in FIG. Transistors are known.

The vertical insulated gate bipolar transistor shown in FIG. 3 has a collector electrode 16, a collector region 18, a highly doped drift region 17, and a lightly doped base region 19, which are laminated in this order. A high concentration base diffusion region 20 is formed therein. An emitter diffusion region 13 is further formed within this high concentration base diffusion region 20, and a polysilicon gate electrode 14 parallel to the low concentration base region 19 is provided between the high concentration base diffusion regions 20 with a gate insulating film interposed therebetween. Patterned. These polysilicon gate electrodes 14 are insulating films and emitter electrodes 1
Insulated from 5.

On the other hand, regarding the lateral insulated gate bipolar transistor shown in FIG. 4, only the numbers given to the corresponding structure of the vertical insulated gate bipolar transistor shown in FIG. 3 will be given and the explanation will be omitted.

When manufacturing the above conventional insulated gate bipolar transistor, after forming the polysilicon gate electrode 14, double diffusion is performed using the self-line method using the polysilicon gate electrode 14 as a mask, and a channel region is formed under the gate electrode 14. was formed to obtain a so-called DSA structure.

FIG. 5 is an equivalent circuit diagram of the above-mentioned insulated gate bipolar transistor, in which a is the emitter electrode, b is the collector electrode, C is the gate electrode, Rb is the base resistance of the high concentration region directly under the channel part, and Rp represents the base resistance of the high concentration region, Rch represents the channel resistance, and R represents the base resistance of the low concentration region.

[Problems to be Solved by the Invention] However, since the conventional insulated gate bipolar transistor described above forms a DSA type MOS transistor, the resistance R shown in the equivalent circuit in FIG.
There is a problem in that b cannot be made small, and a voltage drop across this resistor occurs due to the minority carrier effect, causing a parasitic transistor to turn on, causing a latch-up phenomenon, and destroying the bipolar transistor.

Furthermore, in the conventional example, since the conductivity type of the channel region matches the conductivity type of the lightly doped base region 19, the MOS has a channel region of the conductivity type opposite to that of the lightly doped base region 19.
) There was also the problem that it was not possible to form a transistor, and there were restrictions on the configuration of an integrated circuit using such an insulated gate type bipolar transistor.

[Means for solving the problems] The insulated gate bipolar transistor according to the present invention has the following features:
a base region formed on the surface of a semiconductor substrate of a first conductivity type; a collector region of a second conductivity type formed in the semiconductor substrate; a base region formed on the surface of the semiconductor substrate and separated from the collector region; an emitter region of a second conductivity type;
a field effect transistor; and an offset gate formation region formed adjacent to the emitter region, which together with the emitter region provides a channel region of the field effect transistor, and which faces the gate electrode of the field effect transistor via a gate insulating film. It is characterized by having the following.

[Example] Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a sectional view showing the structure of the first embodiment of the present invention. In the figure, 1 is a semiconductor substrate of a first conductivity type, and an emitter of a second conductivity type is provided on the surface of the semiconductor substrate 1. Diffusion area 2
A base diffusion region 3 and a highly doped back gate region 11 are formed.

A collector diffusion region 4 of a second conductivity type is formed in the base diffusion region 3, and an emitter contact hole, a collector contact hole, and a base contact hole are formed in the insulating film covering the surface of the semiconductor substrate 10. Emitter electrode 7, collector electrode 8, and back gate electrode 12 are connected to emitter region 2, collector diffusion region 4, and back gate region 11, respectively, through these contact holes.

Offset gate formation region 9 adjacent to emitter region 2
A polysilicon gate electrode 5 is provided above with a thin gate insulating film interposed therebetween, and a glabellar insulating film 6 is interposed between the gate electrode 5 and the emitter electrode 7. Therefore, the channel of the field effect transistor including the gate electrode 5 can be made into an offset gate type, and the resistance component can be reduced, which was impossible with conventional double diffusion.
Latch-up phenomenon can be prevented. Furthermore, a channel having a conductivity type opposite to that of the semiconductor substrate can also be formed.

FIG. 2 is a sectional view showing the structure of a second embodiment of the present invention. Components having the same configuration as those in the first embodiment are given only the same numbers and their explanations will be omitted. In FIG. 2, reference numeral 10 denotes a heavily doped shield base region including a portion where the offset gate formation region 9 is formed.
prevents the parasitic transistor from turning on. Therefore, in this embodiment, the breakdown resistance can be further improved than in the first embodiment.

[Operations and Effects of the Invention] As explained above, in the insulated gate bipolar transistor according to the present invention, the channel region of the field effect transistor is configured with the offset gate formation region together with the emitter region to have an offset structure. The impurity concentration of regions other than the region can be set arbitrarily, and the resistance of this region can be lowered. Therefore, the latch-up phenomenon of parasitic transistors can be prevented,
The effect of preventing destruction of the transistor can be obtained. Furthermore, since the conductivity type of the channel can be determined regardless of the conductivity type of the substrate, when used as a component of an integrated circuit, the degree of freedom in circuit configuration can be improved.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view showing the structure of a first embodiment of the present invention, FIG. 2 is a cross-sectional view showing the structure of a second embodiment of the present invention, and FIG. 3 is a cross-sectional view of a conventional vertical insulated gate bipolar transistor. FIG. 4 is a cross-sectional view showing the structure of a conventional lateral insulated gate bipolar transistor, and FIG. 5 is an equivalent circuit diagram of the conventional insulated gate bipolar transistor. DESCRIPTION OF SYMBOLS 1... Semiconductor substrate, 2... Emitter diffusion region, 3... Base diffusion region, 4... Collector diffusion region, 5...... Gate electrode, 6... Interlayer insulating film, 7... Emitter electrode, 8... Collector electrode [i, 9... Offset gate formation region, 10...・・・
・High concentration shield base area. Patent Applicant: NEC Corporation Agent Patent Attorney Kiyoshi Kuwai - Figure 1 Figure 2 Figure 1b Figure 3 Figure 4 Figure 5

Claims (1)

[Scope of Claims] A base region formed on a surface portion of a semiconductor substrate of a first conductivity type; a collector region of a second conductivity type formed on the semiconductor substrate; a collector region formed on a surface portion of the semiconductor substrate; In an insulated gate bipolar transistor comprising an emitter region of a second conductivity type separated from a collector region, and a field effect transistor in which the emitter region is a part of a channel region, an emitter region formed adjacent to the emitter region An insulated gate bipolar transistor further comprising an offset gate forming region which together with the field effect transistor provides a channel region of the field effect transistor and faces a gate electrode of the field effect transistor with a gate insulating film interposed therebetween.