JPS6330077U

JPS6330077U -

Info

Publication number: JPS6330077U
Application number: JP12033886U
Authority: JP
Priority date: 1986-08-07
Filing date: 1986-08-07
Publication date: 1988-02-27

Description

[Brief explanation of the drawing]

第１図は本考案の画面表示回路の一実施例を示
すブロツク図、第２図は第１図の回路におけるキ
ヤラクタの配列を示す説明図、第３図は第１図に
用いられている水平同期信号抜取り回路の一実施
例を示すブロツク図、第４図は第１図の回路によ
つて画面に表示されるキヤラクタの一例を示す説
明図、第５図はクロツク発生回路の一実施例を示
すブロツク図、第６図は従来例の画面表示回路を
示すブロツク図、第７図は第６図の回路における
画面に表示されるキヤラクタ配列を示す説明図、
第８図は１５ＫＨｚ帯の水平同期信号でインター
レースで画面に表示されたキヤラクタと３１ＫＨ
ｚ帯の水平同期信号でノンインターレースで画面
に表示した表示例を示す説明図である。１１……水平同期信号抜取り回路、１２……キ
ヤラクタ発生回路、１３……クロツク発生回路、
１４……制御回路、１５……切換回路、１６……
ＣＲＴ。 Fig. 1 is a block diagram showing one embodiment of the screen display circuit of the present invention, Fig. 2 is an explanatory diagram showing the arrangement of characters in the circuit of Fig. 1, and Fig. 3 is a horizontal FIG. 4 is an explanatory diagram showing an example of the characters displayed on the screen by the circuit of FIG. 1. FIG. 5 is a block diagram showing an example of the synchronous signal sampling circuit. 6 is a block diagram showing a conventional screen display circuit, FIG. 7 is an explanatory diagram showing a character arrangement displayed on the screen in the circuit of FIG. 6,
Figure 8 shows a character displayed on the screen in interlace with a 15KHz horizontal synchronization signal and a 31KH signal.
FIG. 3 is an explanatory diagram showing an example of a display displayed on a screen in a non-interlaced manner using a Z-band horizontal synchronization signal. 11...Horizontal synchronization signal extraction circuit, 12...Character generation circuit, 13...Clock generation circuit,
14...Control circuit, 15...Switching circuit, 16...
C.R.T.

Claims

[Claims for Utility Model Registration] 1. A television signal whose horizontal scanning frequency has been doubled is input, and a horizontal synchronization signal sampling circuit that converts every other horizontal synchronization signal from the television signal; , a character generation circuit that generates character data to be displayed on the front screen of a television receiver; a control circuit that outputs a character code to the character generation circuit; and character data output from the character generation circuit. If the horizontal scanning frequency is fH, the number of dots in the horizontal direction of a character is m, and the natural number representing the size factor of the displayed character is n, then fH× m×
a clock generation circuit that generates a clock signal for character display with a frequency of n/2, and a character data multiple output means that outputs horizontal character data twice each to be output to the switching circuit side. A screen display circuit comprising: 2. The screen display circuit according to claim 1, wherein the clock generating circuit includes a PLL feedback loop that compares the phase with a horizontal synchronizing signal and follows the horizontal synchronizing signal.