JPS63304794A - Parallel expansion type time division switch circuit - Google Patents

Abstract

PURPOSE:To reduce the number of data memories by sequentially selecting and outputting data to outputting side highways from memory modules excepting those in the middle of writing. CONSTITUTION:(n+1)-Number of memory modules 41-43 consisting of (n)- number of data memories which respectively corresponds to (n)-number of input side highways in one by one, and of a selector selecting the signal of one system from the output signals of (n)-number of control memories, a write control circuit 31 which controls to sequentially select one among the memory modules 41-43 and to sequentially write data in (n)-number of the input side highways, and (n)-number of selectors 14 and 15 which select and output data from (n)- number of memory modules excepting the memory modules 41-43 in the middle of writing to the output side highways. Thus, the number of data memories constituting a switching circuit can be reduced.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a time division switch circuit for setting the route of a line or a line bundle, and particularly for setting the route of a large capacity line or line bundle. The present invention relates to a parallel expansion type time division switch circuit suitable for.

[Conventional technology]

The circuit is a conventional parallel expansion type time division switch.

Published by NTT, Research and Practical Application Report, Volume 29, No. 11 (198
0), pp. 1952-1953.

Although the parallel expansion type time division type switch circuit has a complicated configuration method, it is possible to increase the number of accommodated lines while always satisfying the non-block connection characteristics. In the prior art, as stated in the above-mentioned document, '['5SI (Time 5lot
5equenoe Integrit7: In order to ensure that the bit string order within one line is preserved after line editing, a double buffer memory format is usually used for time division switches. There are two ways to implement double buffer memory: "serial format" and "parallel format." The latter allows switch operation even when the memory operation speed is slower, so it is recommended when the number of lines accommodated is large. teeth,"
``Parallel format'' is advantageous. For this reason, a "parallel type" double buffer memory format is used in a parallel expansion type time division switch circuit that aims to increase the number of lines that can be accommodated.

[Problem that the invention seeks to solve]

In the above conventional technology, when configuring a circuit of n-parallel parallel expansion type time division switches, in order to prevent contention when accessing the data memory on the data read side, n parallel highways are Allocating data memory.

Therefore, in n parallel.

The number of ℃ data memories is 2 depending on the double buffer memory format.
Including doubling, the total number of data memories required is 2.
There will be XnXn pieces. Therefore, there is a problem that the cost of the switch circuit is high.

SUMMARY OF THE INVENTION An object of the present invention is to reduce the number of data memories constituting the switch circuit and to provide an economical parallel-deployed time division switch circuit.

[Means for solving problems]

The above purpose is to provide one-to-one access to n input highways
n + 1 memory modules each consisting of a selector that selects one system of signals from the output signals of the corresponding n data memories and n control memories in a timely manner; and one of the memory modules is sequentially selected. a write control circuit that controls sequential writing of data on the n input highways; and n memory modules that selectively output data from the n memory modules excluding the memory module in the process of writing to the n output highways. This is achieved by providing a selector.

[Effect]

The write control circuit sequentially selects one memory module from among the n+1 memory modules and sequentially writes data on the n input highways. Here, since the memory module is composed of n data memories in one-to-one correspondence with n input highways, all input data can be stored. The read operation is performed on the remaining n memory modules, and a selector in the memory module selects the output n
It is connected in one-to-one correspondence to a control memory that stores the output order of the data of the book highway, and is read out according to the data in the control memory. Furthermore, the n selectors connected to the output highway select the signals of the memory modules that have selected the control memories that correspond one-to-one to each selector, and output the selected signals to the output highway.

There are n + 1 memory modules, and if we focus on a particular memory module, the phase of operation of the memory module is divided into n + 1 phases with equal periods, one of which is a write operation, The remaining n phases are read operations. Here, by sequentially selecting Cn control memories from the first to the nth by the selector in the memory module,
Data stored during the write operation can be arbitrarily read from n highways in n phases.

Therefore, as long as the method of sequentially selecting memory modules in a write operation and the method of sequentially selecting a control memory in a read operation always follow a certain rule, the TSSI can be preserved and non-blocking switching characteristics can be achieved.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a configuration diagram of a parallel expansion type time division switch circuit according to a first embodiment of the present invention. The parallel expansion type time division switch circuit of this embodiment includes memory modules 41 to 43 that temporarily store data input to the eight highway 1 (HWl) and highway 2 (HI3), and write operations of the memory modules 41 to 43. From the outputs from the write control circuit 61 that controls, the control memories 21 to 22 that control read operations from the memory modules 41 to 43, and the memory modules 41 to 43, the output highway 1
(HW1') and highway 2 (HW2').

Furthermore, the memory modules 41 to 43 described above receive one system of control signals from the data memory 1 for storing HWl data, the data memory 2 for storing HI3 data, and the control memories 21 to 22. It is comprised of a selector 11 which selects and applies it to the data memory 1.2. Further, regarding the memory module 42, a data memory 5 for storing data of HW1, HI
3 data memory 4 and control memory 21
It consists of a selector 12 which selects one system of signals from the control signals from 22 to 22 and applies it to the data memory 3.4. Furthermore, regarding memory module 43&C, HWl
One system of signals is selected from the control signals from the data memory 5 storing the data of HI3, the data memory 6 storing the data of HI3, and the control memories 21 to 22, and the data memory 5
, 6.

Next, the operation of this embodiment will be explained using the time chart of FIG. Hereinafter, the basic temporal period in which the time slot switching operation is performed will be referred to as a frame.

In a certain frame, the memory module 41 is in a write state, and the data memories 1 and 2 are in a state of a data write operation of HW1 and a data write operation of HI3 on the switch input side, respectively. Write operations to the data memories 1 and 2 are performed sequentially from the beginning of the address of the data memory according to a control signal from the write control circuit 31. At this time, the data memories 3 and 4 are in a read operation to the selector 15, and the data memories 5 and 6 are in a read state to the selector 14. The read operation to the selectors 14 and 15 is performed from the output control signals from the control memory 21 that stores the designation information of the read address to the selector 14 and the control memory 22 that stores the designation information of the read address to the selector 15, respectively. , the output control signal of the control memory 21 selected by the selector 15 and the output control signal of the control memory 21 selected by the selector 12
It is executed randomly according to the output control signal of No. 2. This is the operation in frame 1 in FIG.

Next, after the operation in frame 1 described above is completed, the memory module 42 enters the write state, and the data memory 5
HWl:td and HI3 data are written to frames 1 and 4, respectively, in the same way as in frame 1. Furthermore, the memory modules 43 and 41 each have a selector 15
And a read operation to the selector 14 is performed. At this time, memory module 43 and memory module 41 perform random read operations according to control signals from control memory 22 and control memory 21, respectively.

This is the operation at frame 2 in FIG. After the operation in frame 2 is completed, in frame 3, memory module 43 enters the write state, and memory modules 41 and 42 respectively.

This is a read operation to the selector 15 and the selector 14. In actual operation, one or more operations of frames 1 to 5 are periodically repeated.

Through the operations described above, data written in, for example, data memories 1 and 2 in a certain frame is read out from data memory 1 in accordance with the read control information of control memory 21 in the next frame, and then passed through selector 14. After two frames, it is read out from the data memory 2 according to the read control information of the control memory 22, and then passed through the selector 15 and output to the HW 1'.
2'. Therefore, the present invention makes it possible to reduce the number of data memories configuring a parallel expansion type time-division switch circuit from 8 in the prior art to 6 while maintaining non-blocking characteristics and guaranteeing TSSI. becomes.

FIG. 3 is a configuration diagram of a parallel expansion type time division switch circuit according to a second embodiment of the present invention. This embodiment is a case of two parallel circuits. The parallel expansion type time division switch circuit of this example is as follows:
Memory modules 141 to 146 that temporarily store data input to HWl and HI3, a write control circuit 31 that controls write operations of the memory modules 141 to 143, and a control memory that controls read operations from the memory modules 141 to 143. 921.22 and the outputs from memory modules 141 to 143, HW1'
and I(W2').

The write control circuit 31 and control memories 21 and 22 are similar to those in the first embodiment. However, in this example,
The memory module 141 includes data memories 1 to 2 that store data of HWl and HI3 and a control memory 21.2.
In addition to the selector 11 that selects one system from two output control signals, a selector 116 is provided that selects one system of data from the output data from the data memories 1 and 2 and outputs it to the selectors 114 and 115. Similarly, the memory module 142 is composed of the data memories 3 and 4, the selector 12, and the selector 117.
are data memories 5, 6, selector 15, and selector 11.
Consists of 8.

The operation of this embodiment is similar to that of the first embodiment, and operates according to the time chart shown in FIG. The feature of this embodiment is that selectors 115, 117, 11 are provided in the memory module.
8, it is possible to reduce the number of signal lines extending between the memory module and the selectors 114 and 115 connected to the output highway.

Although the above two embodiments are cases in which n = 2, that is, two parallel circuits, the present invention is not limited to this, and it goes without saying that it will work effectively even in cases where n≧3.

〔Effect of the invention〕

According to the present invention, in an n-parallel parallel expansion type time division switch circuit, the number of data memories is reduced to 2Xn compared to the conventional technology.
The number can be reduced from 2 to n2+n, which has the effect that the circuit can be constructed economically.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram of a two-parallel expanded type time division switch circuit according to the first embodiment of the present invention, FIG. 2 is an operation timing chart, and FIG. 3 is a two-parallel expanded type according to the second example of the present invention. FIG. 2 is a configuration diagram of a time division switch circuit. 1-6...Data memory, 11-15, 114
~118...Selector, 21.22...
- Control memory, 51...Writing control circuit, 4
1-43, 141-143...Memory module.

Claims (1)

[Claims] 1. n multiplexing levels that output data of any time slot of any highway among the input multiplexing level highways of n (n: an integer of 2 or more) In a parallel expansion type time division switch circuit that switches to any time slot of any highway in the highway, n control memories each control an output data string in one-to-one correspondence with the highway on the output side. and n+1 data memories, each corresponding to n input highways, which temporarily store data, and a selector which selects one system of signals from the output signals of the n control memories at the appropriate time. a memory module, a write control circuit that sequentially selects one of the memory modules and controls it to sequentially write data on the input highway; A parallel expansion type time division switch circuit comprising one selector that sequentially selects and outputs data to the output highway of the circuit. 2. Each of the memory modules includes a selector that selects one system of output data from n systems of output data of the n data memories and applies the voltage to the selector that selects and outputs the data to the output highway. A parallel expansion type time division switch circuit according to claim 1.