JPS63307565A - Channel processor - Google Patents

Abstract

PURPOSE:To decrease the number of signal lines by providing a reserve bit part in response to each channel device to store the information on the using state of the channel device and replacing the contents of said reserve bit part to secure the right of priority for application of channel devices. CONSTITUTION:A reserve bit means 13 is set in a channel processor 11 in response to each channel device 12. The device 12 can replace the reserve bit via a bus line and the processor 11 can replace directly the reserve bit. Then the processor 11 or the device 12 replaces the reserve bit before a start or interruption process to acquire the processing priority. If the device fails to acquire the priority, the state or interruption process is discontinued. Thus it is possible to decrease extremely the number of signal lines set between the processor 11 and the device 12.

Description

[Detailed Description of the Invention] [Summary] The present invention provides a channel processing device with a reserve bit section for storing information indicating the usage state of each channel device, and the channel processing device stores information indicating the usage state of the channel device. When any of the channel devices is activated, or when any of the channel devices requests processing to the channel processing device, the contents of the reserved bit section are updated to ensure usage priority.

[Industrial application field]

The present invention relates to a channel processing device in a large-scale computer system, and in particular to a main storage unit (MSU) and an input/output unit (I10) based on instructions from a central processing unit (CPU).
Channel processing device (C
HP), a channel device that performs direct data transfer with Ilo! (Related to control between CF(E) and CHPO that executes various processes of multiple CHEs.

[One conventional technique] FIG. 5 is a connection diagram between CHP and CHE in the conventional technique. In the figure, 41 is a channel processing device (C
HP), 42 is a plurality of (0 to n) channel devices (CH
E), and between the CHP and each CHE are a bus line DB, a plurality of selection signal lines 11, and response signal lines 1. , and an interrupt signal line I13. Normally, the CHP performs integrated processing for the entire system, and the CHE performs 110 individual processes. As shown in FIG.
Information is transferred between the CPU (SU) and the central processing unit (CPU) under the control of the storage control unit (MCU).

The processing procedure between the CHP and each Cf(E) may be as follows: (1) When the boot from the CHP to the CHE is successful; (2) When the boot from the CHP fails; (3) This is a case where the CHE requests the CHP for processing.In the case of (1), when the CPU sends an input/output command to the CHP, the CHP transmits the channel selection signal (SELO to SEL n ) to the corresponding CHE. When the CHE is able to accept the input/output command, the CHE returns a response signal (ACPTO~^CPTn) to the CHP.CI(P determines that activation is successful if the response signal is returned within a certain period of time. The necessary information for the input/output command is sent to CI (E) via the bus line DB.In case (2), a channel selection signal is sent to CHE in the same way as in (1), but if CHE is in use. Therefore, if a response signal is not returned within a certain period of time, the CHP considers the CHE to be "busy." In the case of (3), the CHE sends a
When requesting processing from P, first send the processing details to bus line D.
Send to CHP via B. Then, a CHE interrupt signal (INTO to 1NTn) is sent out, and when the CHP detects this interrupt signal, it refers to the process contents that have already been sent out and executes the process.

[Problem that the invention seeks to solve]

The conventional configuration described above has the following problems. That is, (1) there are usually 16 to 256 CHEs under each group, as shown in Figure 3, under one CHP.
is connected. Therefore, if selection signal lines, response signal lines, interrupt signal lines, etc. are connected in correspondence with CHE, the number of signal lines becomes extremely large.

(2) In order to connect a large number of CHEs, CHPs and CHEs are connected via one or two stages of bus adapters. Therefore, the propagation time of the channel selection signal and response signal is long. This increases the time it takes for the CHP to investigate the busy state of the CHE, reducing the efficiency of CHP usage. (3), C) Starting CH&' from IP, and C
) Since the processing requests from IB to CHP are controlled separately, there is a difference in processing between the two. At this time, the CHE has the right to decide which process to perform, and the CHE's processing request always takes priority. For this reason, c [
CHE startup processing from t p often fails (C
HP usage efficiency is getting worse.

[Means and operations for solving the problems] The present invention provides a channel treatment device that solves the above-mentioned problems.According to the present invention, the channel treatment device (11)
A reserve bit means (13) as a relay means is provided corresponding to each channel device 12 (0 to n), and this reserve bit can be updated from the channel device via a lotus wire, and the channel processing device allows to update this reserve bit directly. Then, the channel processing device or channel device updates the reserve bit before start-up processing or interrupt processing to obtain processing priority. If priority cannot be obtained, processing such as canceling startup processing or interrupt processing is performed.

〔Example〕

FIG. 1 is a schematic configuration diagram of a channel processing device according to the present invention and a connection diagram between the channel device. In Figure 1,
11 is a channel processing device (CHP), 12 is a plurality of devices (0 to
The channel device (CHE) 13 of n) is a reserved bit section provided in C'IIP. CHP and each CH
EOs are interconnected only by bus line DB. Each of the reserved bit sections 13 is composed of, for example, a 2-bit flip-flop (not shown), and corresponds to each CHE.
, -11, 2 bits each are prepared. Here C
It PR is a reserved bit for CHP and CIIE
R is a reserved bit for CHE. This reserved bit can be updated from the CHE via the bus line DB, and can be updated directly from the CHP. As is clear from the figure, the selection signal line, response signal line, and interrupt signal line used in the past are completely unnecessary, and the bus line D
Commands are issued via B only.

Transmission and reception of signals according to the present invention will be explained in detail below with reference to FIG.

FIG. 2 is a transition diagram illustrating the states of reserve bits. Each of the reserved bits (0 to n) is 4 as shown in the figure.
It can take two states.

When CIIPR is "0" and CIIER is "0", that is, "o o" indicates that neither has taken priority, "Ol" indicates that CHE has taken priority, “10” indicates that CHP has taken priority;
"11" indicates that the CHE has the priority, but the CHP is reserved to take the priority after the processing is completed. Here CIl, CIIP on the arrow.

CIIP/C11 etc. indicate that CHE updates, CHP updates, and CIIP or CHE updates, respectively.

In such a state, starting from the CHP is first performed as follows. Input/output commands from CP LJ to CH
When sent to P, CHP changes the reserved bit from “OO” to “10’. In this case, the reserved bit changes to “00”.
” (for example, “Obi”), startup will fail. That is,
As mentioned above, when it is other than "00", it indicates that either CHP or CHE has priority.
CH only when the reserved bit is in the state of '00'
P can take priority. Information necessary for an input/output command is sent from the CHP to the CHE corresponding to the reserved bit for which the CHP has obtained priority via the bus vADB. The CHE executes input/output commands from the CHP and sends the responses to the CHP via the bus line.

At this time, the reserved bit of this CHE is "10". When the CHP receives a response from the CHE, it changes the reserve bit from "10" to "00" and the process ends.

Next, when the CHE requests the CHP to perform processing, the CHE sends the processing details to the CHP via the bus line. At this time,
At the same time, change the reserved bit from 00 to 0 bit. If the reserved bit is other than "002" (for example "10")
The CHE is notified of the interrupt failure. And CHP is C
When the processing requested by the HF is executed, the processing result is sent to the CHE via the lotus wire, and the reserve bit is set to “01”.
” to “OO”. Also, when C) IF receives the asynchronous status of the input/output device, it first changes the reserve bit from “00” to “Ol” to take priority and output the input/output device (110 ) and requests the CHP for processing.

FIG. 3 is a configuration diagram of a system to which the present invention is applied, in which a memory control unit (MCU) receives input/output commands from a central processing unit (CPU), and a main storage unit (MSU).
), write to and read from the channel processing unit (CHP
) and the data transfer of the channel device (CHE). As mentioned above, one CHP has more than 10 CHEs.
It controls multiple groups of CHF. The present invention aims to improve the efficiency of the control procedure between the CHP and these CHEs, and as shown in FIG.
The number of signal lines between HP and CHE can be significantly reduced. FIG. 4 is a block diagram of the CHP shown in FIG. 3. As mentioned above, the reserve bit section 13 is divided into a plurality of reserve bits (0 to n), and from the CHE via the port (PORT), the reserve bit section 13 is divided into a plurality of reserve bits (0 to n). 111 circuit (R3VC), CHP processing unit (CIIP
C) is updated directly. In addition, data transfer between the CHE and the MCU is performed by each port and CHP processing unit (
CIIPC).

[Power of invention]

As explained above, according to the present invention, CHP and CHE
The number of signal lines between the
Since the CHP can easily refer to the busy state of the CHE, the usage efficiency of the CHP is greatly improved, and furthermore, it is possible to prevent mismatch between activation from the CHP and interrupt processing from the CHE.

[Brief explanation of the drawing]

Fig. 1 is a basic configuration diagram according to the present invention, Fig. 2 is a state transition diagram of the reserved bit section in Fig. 1, Fig. 3 is a system configuration diagram to which the present invention is applied, and Fig. 4 is Fig. 3 Channel processing The block diagram of the device and FIG. 5 are conventional configuration diagrams. (Explanation of symbols) 11, 41... channel processing device, 12, 42...
... Channel device, 13... Reserve bit section. Configuration diagram of the present invention Fig. 1 CHP...Channel processing device C) - IE... Channel device State transition diagram of reserved bits of the present invention Fig. 2 System configuration diagram to which the present invention is applied Fig. 3 Memory co/ (MOlJ) Channel processing device detailed block diagram Figure 4 Conventional configuration diagram Figure 5

Claims (1)

[Claims] 1. In a channel processing device that has a plurality of channel devices that control data transfer between a main storage device and an input/output device and controls the channel devices via a bus line, the channel A relay means is provided for storing information indicating a usage state corresponding to each of the devices, and when the channel processing device activates any of the channel devices via the bus line, or when any of the channel devices A channel processing device characterized in that when requesting processing to the channel processing device, priority of use is secured by updating the contents of the relay means.