JPS633162U - - Google Patents
Info
- Publication number
- JPS633162U JPS633162U JP1986095844U JP9584486U JPS633162U JP S633162 U JPS633162 U JP S633162U JP 1986095844 U JP1986095844 U JP 1986095844U JP 9584486 U JP9584486 U JP 9584486U JP S633162 U JPS633162 U JP S633162U
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- packaged
- overlap
- whole
- utility
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/531—Shapes of wire connectors
- H10W72/536—Shapes of wire connectors the connected ends being ball-shaped
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
- H10W90/722—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between stacked chips
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
- H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink
Landscapes
- Wire Bonding (AREA)
Description
第１図はこの考案の一実施例による半導体装置
を示す図、第２図はその斜視図、第３図は従来装
置を示す図である。 ５……上側のチツプ、６……下側のチツプ、７
……ワイヤボンド、８……ハンダバンプ、９……
パツド。
を示す図、第２図はその斜視図、第３図は従来装
置を示す図である。 ５……上側のチツプ、６……下側のチツプ、７
……ワイヤボンド、８……ハンダバンプ、９……
パツド。
Claims (1)
- 異なる２つのチツプを重なるよう配置し、両者
を電気的に接続し、全体をパツケージしてなるこ
とを特徴とする半導体装置。
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1986095844U JPS633162U (ja) | 1986-06-23 | 1986-06-23 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1986095844U JPS633162U (ja) | 1986-06-23 | 1986-06-23 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS633162U true JPS633162U (ja) | 1988-01-11 |
Family
ID=30960928
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1986095844U Pending JPS633162U (ja) | 1986-06-23 | 1986-06-23 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS633162U (ja) |
-
1986
- 1986-06-23 JP JP1986095844U patent/JPS633162U/ja active Pending