JPS6334544B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a digital signal processing device suitable for use in an audio signal recording and reproducing device using the PCM method, for example, which PCM-modulates an audio signal and uses a VTR (video tape recorder) as a transmission medium. .

An outline of such a signal recording/reproducing apparatus is shown in FIG. In Fig. 1, 1 is, for example, a rotating two-head type.
Showing a VTR. This VTR 1 supplies a video signal given from its recording signal input terminal 1i to a pair of rotating magnetic heads via a recording system consisting of an FM modulator, etc., and records one field of the video signal on a magnetic tape as an inclined track. It is something. Further, a video signal formed by passing a signal reproduced from a magnetic tape through a reproduction system including an FM demodulator and the like is outputted to a reproduction signal output terminal 1o of the VTR 1. This VTR 1 generally has a feature of a wider transmission band than a fixed head type, and is used to record and reproduce a PCM signal whose signal format is the same as that of a video signal.

That is, 2L and 2R are terminals to which left and right signals of the stereo audio signal are supplied, respectively, and these left and right signals are supplied to low-pass filters 3L and 3R, sampling and hold circuits 4L and 4R, and AD conversion, respectively. PCM modulation is performed by passing the signal through the receivers 5L and 5R. Since the digital outputs of the AD converters 5L and 5R are parallel codes, they are converted into a serial format by the parallel-serial converter 6.
The time axis compression circuit 7 is supplied to the time axis compression circuit 7.
The output of the synchronizing signal adding circuit 8 is supplied to the synchronizing signal adding circuit 8. The time axis compression circuit 7 and the synchronization signal addition circuit 8 convert the PCM signal into the same signal form as the video signal.The former creates a data missing period corresponding to the vertical blanking period in the video signal, and the latter creates a A synchronization signal corresponding to the vertical synchronization signal and horizontal synchronization signal in is added. The output of this synchronizing signal addition circuit 8 is supplied to the recording signal input terminal 1i of the VTR 1.

That is, Fig. 2 shows one field period (262.5H, where H is the horizontal period) of this recorded PCM signal, and the vertical synchronization signal VD, equivalent pulse EQ ₁
No data is inserted in the vertical blanking period of 8H including EQ ₂ and the period before and after it. For example,
During the 245H period, one block of the PCM signal is inserted every 1H period defined by the horizontal synchronization signal HD. As shown in an enlarged view in FIG. 3, this one block of PCM signal starts after the period IBG including the horizontal synchronizing signal HD with a pulse width equivalent to 8 bits and the subsequent backport with a pulse width equivalent to 8 bits.
Each word consists of three words of 32-bit code inserted, and the period of 1H is equivalent to 112 bits. This one word consists of left and right audio signals of 16 bits arranged in series, and for the sake of simplicity, FIG. 3 shows a case where "1" and "0" alternate. In addition, as shown in Fig. 4, the vertical blanking period has a 1/2H shift in the odd and even fields, similar to the television signal, and the equivalent pulse EQ ₁ for the 3H period, EQ 1 for the 3H period. Equivalent pulse of vertical synchronization signal VD and period of 2H
EQ ₂ is consecutive. And P.C.M.
The period of 245H from the time when the signal is first inserted in that field is the period in which the PCM signal exists, and the period after this until the PCM signal is inserted at the beginning of the next field is the data missing period IRG. , (245H+IRG) is called one record. The data missing period IRG is 17H in even fields and in odd fields.
It is 18H, and the average is 17.5H.

During playback, a PCM signal similar to that shown in FIG. 2 is supplied to the time axis expansion circuit 10 via the synchronization signal separation circuit 9. The output of this time axis expansion circuit is
A PCM signal appears and this is the serial-parallel converter circuit 11
is converted into parallel code by Then, the output terminal 1
A left signal is obtained at the output terminal 4L, and a right signal is obtained at the output terminal 14R.

The time axis compression circuit 7 and the time axis expansion circuit 10 are
This is realized using RAM or multiple shift registers. Further, the recording system is provided with a reference oscillator (not shown), and from the output of the reference oscillator, sampling pulses to the sampling hold circuits 4L and 4R are generated.
Clock pulses for AD converters 5L, 5R, parallel-to-serial converter 6, and time base compression circuit 7 are formed. On the other hand, in the reproduction system, the synchronization signals HD and VD separated from the reproduction PCM signal are used as time bases, and the time axis expansion circuit 10, serial parallel converter 11, and DA
Clock pulses are generated for transducers 12L and 12R.

In such a recording/reproducing device, the time axis compression circuit 7
The time axis expansion circuit 10 performs compression and expansion processing of the time axis in units of one record, for example.
Can be configured by RAM. Furthermore, the control of the RAM is devised so that writing and reading are performed asynchronously in order to convert the time axis. And the RAM that constitutes the time axis compression circuit 7
The capacity of the RAM constituting the time axis expansion circuit 10 is determined in consideration of the amount of time axis expansion and the amount of time axis fluctuation occurring in the VTR 1. However, if this amount of time axis variation exceeds initial expectations, overflow or underflow will occur. Therefore, countermeasures against overflow or underflow are required. One of the countermeasures is to compare the contents of the write address counter and read address counter for the RAM, detect a match between the two outputs as an overflow or underflow, and use this detection to clear the write address counter or read address counter. Writing and reading were restarted from the beginning of one record. However, this method has the problem that in the worst case, there is a risk that there will be no signal for about one field period (16.7 msec), and the signal after correction will be considerably distorted.

Therefore, the applicant has devised a system in which the clock supply to the address counter of the RAM is stopped when the possibility of an overflow or underflow is detected first, thereby preventing the no-signal state from becoming prolonged as described above. proposed a device that corrects the signal using a signal from a nearby point in time. In this case, when an overflow is about to occur, the write clock supply is stopped, the write address no longer advances, the PCM signal is written to the same address redundantly, and only the read address advances, so that the read address cannot be read. A part of the PCM signal is missing. Conversely, when an underflow is about to occur, the read clock supply is stopped and the read address does not advance, and the PCM signal at the same address is read repeatedly, so the read PCM signal remains the same for a part of the period. It becomes something that is held by something. There is a problem in that when signal loss or duplication due to such correction occurs in a place where the signal level changes rapidly, it may be detected.

In consideration of this point, the present invention is designed to vary the frequency division ratio of the PLL circuit for forming the read clock signal when the possibility of overflow or underflow is detected. According to the present invention, overflow or underflow can be prevented without causing dropout or duplication of PCM signals. Although the frequency of the read clock signal, which should originally be constant, changes due to the complementary operation,
Since the change is slight and not sudden, it is practically undetectable.

Hereinafter, one embodiment of the present invention will be described with reference to the drawings. As shown in FIG.
Supplied to the circuit 20W. This horizontal sync signal HD
is supplied to a phase comparator 50, where it is phase-compared with the output of a VCO (voltage-controlled variable frequency oscillator) 52 via a frequency divider 51, and the comparison output is sent to the VCO 52 via a low-pass filter 53 as its control voltage. applied. The cutoff frequency of this low-pass filter 53 is considered to be relatively high, and the write bit clock PWBC generated at the output terminal 21W of the PLL circuit 20W follows the time axis fluctuation called jitter included in the reproduced PCM signal. Become something.

Further, the output of the PLL circuit 20W is supplied via a frequency divider 54 to a PLL circuit 20R for forming a read bit clock PRBC. PLL circuit 2
0R includes a phase comparator 55, a frequency division ratio setting circuit 56 forming a 1/N frequency divider, a VCO 57, and a low-pass filter 58. The cutoff frequency of this low-pass filter 58 is
The read bit clock PRBC generated at the output terminal 21R of the PLL circuit 20R is selected to be extremely low, such as 0.2 to 0.3 [Hz].
It follows extremely low frequency time axis fluctuations called drift included in the PCM signal. In this way, if the read bit clock PRBC that follows the drift is formed by the PLL circuit 20R,
Unlike the case where a constant frequency readout bit clock is used, there is no need to correct drift components, and the memory capacity for removing time axis fluctuations can be reduced. Even if the reproduced audio signal contains drift, it does not have a large effect on the auditory sense.

A frequency division ratio control circuit 59 associated with a frequency division ratio setting circuit 56 that constitutes a 1/N frequency divider of this PLL circuit 20R
are supplied with detection signals G ₁ and G ₂ from a detection circuit 36, which will be described later, and the frequency division ratio (1/N) is changed by these detection signals G ₁ and G ₂ . In addition, the write bit clock PWBC from the PLL circuit 20W is supplied to the word counter 22W, so that the write word clock PWBC is supplied to the word counter 22W.
PWWC is formed and the read bit clock is
A read word clock PRWC is formed by supplying PRBC to word counter 22R.

Further, the reproduction synchronization signal is transmitted to the gate signal generation circuit 23.
This forms a write gate signal PWG that controls the start and stop of a write operation, and also forms a read gate signal PRG that controls the start and stop of a read operation. Since the time axis is expanded in the reproduction system, the write gate signal is
PCM during data missing period IRG due to PWG
Writing of signals to RAM is paused, while
As shown in FIG. 6B, readout is performed continuously in synchronization with a readout clock lower in frequency than the write clock frequency by the readout gate signal PRG. For this reason, a write gate circuit 24W controlled by a write gate signal PWG and a read gate circuit 24R controlled by a read gate signal PRG are provided. The write bit clock PWBC and write word clock PWWC that have passed through the write gate circuit 24W are used as the address counter 2 on the write side.
5W, while the read gate circuit 24R
The read bit clock PRBC and read word clock PRWC that have passed through are supplied to the read side address counter 25R. The outputs of these address counters are supplied to the address selector 26, which selects either the write side or the read side address signal, and the selected address signal is applied to the RAM 27. The PCM signal input to the RAM 27 is synchronized with the write bit clock PWBC by passing through the latch circuit 28.
The PCM signal output from the RAM 27 is serial-parallel converted as described above and sent to the DA converters 12L and 12R.
supplied to

In order to extend the time axis and remove time axis fluctuations using one RAM 27 in this way,
Write and read operations are performed asynchronously.
This is a control signal ADSLCT which is applied to the address selector 26 to control the selection of a write address or a read address, and a control signal WE which is supplied to a write/read control circuit (not shown) of the RAM 27.
made by. These control signals ADSLCT and WE are formed by the memory control signal generation circuit 29 from the write bit clock PWBC and the read bit clock PRBC. That is, a write bit clock PWBC with a period T _W as shown in FIG. 7A.
The control signal WE shown in _FIG . _1C and _the control signal ADSLCT shown in FIG. These control signals WE and
ADSLCT stipulates that the write cycle indicated by t _W and the read cycle indicated by t _R in _FIG . At _R , a PCM signal is read from a predetermined read address.

In this example, the capacity of the digital signal stored in the RAM 27 to be read is detected using the control signals WE and ADSLCT to prevent overflow or underflow from occurring. Therefore, the control signal WE is supplied to the counter 31, and the control signal inverted by the inverter 30 is supplied to the counter 32. These counters 31 and 32 convert the control signal in units of bits into units of words. Furthermore, the pulse width is made short by differentiating circuits 33 and 34, which are constituted by logic circuits, connected to the outputs of these counters 31 and 32. The output of the differentiating circuit 33 is supplied to the reversible counter 35 as its addition input (indicated by UP in the figure), while the output of the differentiating circuit 34 is supplied to the reversible counter 35 as its subtraction input (indicated by UP in the figure).
(indicated by DOWN). The output of this reversible counter 35 is given to a detection circuit 36,
The detection circuit 36 outputs the first detection signal _G1 and the second detection signal G1.
A detection signal _G2 is formed. The detection signal _G1 becomes low level (“0”) when the difference between the write word address and the read word address becomes too large than the first set value, that is, when an overflow is about to occur.
Therefore, the detection signal _G2 becomes "0" when the difference between the two becomes too small below the second set value, that is, when an underflow is about to occur.

Note that the counters 31 and 32 and the reversible counter 3
5 is in a reproduction state and is reset by a reset signal STBY generated at the beginning of the PCM signal of one record.

An example of the above-mentioned detection circuit 36 will be explained using a case where the reversible counter 35 has 6 bits. FIG. 8 shows its configuration, in which the reversible counter 35
The 6-bit outputs a to f are supplied to a decoder 43. The decoder 43 receives the output of the reversible counter 35.
A signal A that becomes “1” when (n=60) for the number when converted to a decimal number (this is set as n);
A signal B that becomes “1” when (n=61) and a signal B that becomes “1” when (n=61),
3) and a signal C that becomes “1” when (n=2).
It generates a signal D that becomes "1" when . In this example, when the output of the reversible counter 35 representing the difference between the write word address and the read word address reaches the first setting value (n=61), that is, (B="1"), only the detection signal _G1 is output. becomes "0" and the output of the reversible counter 35 becomes the second setting value (n=2), that is, (D="1"), so that only the detection signal _G2 becomes "0". I have to.

More specifically, the OR gate 4 is supplied with the signal A from the decoder 43 and the reset signal STBY.
A flip-flop 45 is provided which is set by the output of G.4 and reset by the signal B, and the output of the flip-flop 45 is used as the detection signal _G1 .
In addition, the signal C from the decoder 43 and the reset signal
A flip-flop 48 is provided which is set by the output of the OR gate 46 supplied with STBY and reset by the output of the AND gate 47, and the output of the flip-flop 48 is used as the detection signal _G2 . The AND gate 47 is supplied with the output of a flip-flop 49 which is set by the reset signal STBY and reset by the signal C, and the signal D.

In the configuration shown in FIG. 8, under normal operating conditions, the flip-flop 4 is reset by the reset signal STBY.
5 and 48 are set, the detection signal
Both G ₁ and G ₂ are "1". However, when the difference between the write word address and the read word address becomes large and the output of the reversible counter 35 reaches the first set value (n=61), the signal B becomes "1", the flip-flop 45 is reset, and the detection signal G ₁ becomes “0”. As a result, when the address difference becomes small again (n=60), the signal A
becomes "1", the flip-flop 45 is set, and the detection signal _G1 becomes "1". Due to this change in the detection signal _G1 , it is detected that an overflow is about to occur, and a control operation is performed accordingly.

Conversely, the difference between the write word address and the read word address becomes smaller, and the reversible counter 3
When the output of G.5 becomes the second set value (n=2), the signal D becomes "1", thereby resetting the flip-flop 48, and the detection signal _G2 becomes "0". As a result, when the address difference becomes large again (n=3), the signal C becomes "1".
As a result, the flip-flop 48 is set, and the detection signal _G2 becomes "1". Due to the change in the detection signal _G2 , it is detected that an underflow is likely to occur, and a control operation is performed accordingly. Furthermore, since the reversible counter 35 of the AND gate 47 and the flip-flop 49 is reset by the reset signal STBY, and all of their outputs become "0", the flip-flop 49 remains unused until the signal C becomes "1".
A protection circuit is configured to prevent the 8 from being reset.

These detection signals G ₁ and G ₂ are supplied to the frequency division ratio control circuit 59 described above. When there is a risk of overflow and the detection signal _G1 becomes "0", the frequency division ratio of the frequency division ratio setting circuit 56 is switched to (1/N+P) (where P is a positive integer). As a result, the frequency of the read bit clock PRBC is changed to a frequency division ratio of (1/
Compared to case N), the increase is (N+P/N) times.

Since the read speed increases in this way, the difference between the read address and the write address becomes smaller than the first set value, and thereby the detection signal _G1 becomes high level ("1"). When the detection signal _G1 becomes "1", the frequency division ratio of the frequency division ratio setting circuit 56 is returned to (1/N).

Further, when there is a possibility of underflow and the detection signal _G2 becomes "0", the frequency division ratio of the frequency division ratio setting circuit 56 is switched to (1/N-P). As a result, the frequency of the read bit clock PRBC is reduced by a factor of (N-P/N) compared to the case where the frequency division ratio is (1/N). When the read speed decreases, the difference between the read address and the write address becomes larger than the second set value, which causes the detection signal _G2 to become "1".
Therefore, the frequency division ratio of the frequency division ratio setting circuit 56 is (1/N)
will be returned to.

As is clear from the above description, according to the present invention, overflow and underflow can be prevented without causing any dropout or duplication of reproduced PCM signals. Therefore, when the reproduced PCM signal is demodulated into an audio signal, it is possible to prevent the audio signal from becoming unnatural. Further, although time axis fluctuations temporarily occur in the reproduced audio signal, by selecting the relationship (N>>P), this time axis fluctuation is hardly detected audibly. Furthermore, the non-overlapping control signals WE and
Using ADSLCT has the advantage that the difference between the write address and the read address can be easily detected using a reversible counter.

Note that when changing the frequency division ratio, in addition to changing the frequency division ratio in three stages (1/N+P) (1/N) (1/N-P) as in the above embodiment, the frequency division ratio can be changed using the detection signal G ₁ Or G ₂
may be sequentially changed while is "0". For example, the frequency division ratio may be changed to (1/N+1) (1/N+2), etc. at predetermined time intervals during the period (G ₁ =“0”).

[Brief explanation of the drawing]

Figure 1 is a block diagram of an audio signal recording and reproducing apparatus using the PCM method to which the present invention can be applied;
3 and 4 are waveform diagrams used for the explanation, FIG. 5 is a block diagram of an embodiment of the present invention, FIGS. 6 and 7 are waveform diagrams used for the explanation, and FIG.
The figure is a block diagram of an example of a detection circuit. 1 is VTR, 9 is sync separation circuit, 20R, 20
W is a PLL circuit, 22W and 22R are word counters, 26 is an address selector, 27 is a RAM, 2
9 is a memory control signal generation circuit, 35 is a reversible counter, 36 is a detection circuit, and 56 is a 1/N frequency dividing circuit.

Claims (1)

[Claims] 1. A digital signal processing device comprising a memory means, which writes a digital signal into a predetermined location of the memory means in response to a write clock signal, reads out the digital signal written in the memory means, and reads out a clock signal in response to the clock signal. The read clock signal is formed by a PLL circuit having a frequency division ratio setting circuit, and further includes signal read capacitance detection means for detecting the capacitance of the digital signal written in the memory means to be read. A digital signal processing device characterized in that the frequency division ratio set by the frequency division ratio setting circuit is controlled based on the output signal of the capacitance detection means.