JPS633515A - Digital phase synchronization circuit - Google Patents

Abstract

PURPOSE:To generate an output signal without phase error in accurately synchronizing with the edge of a reference pulse by using a data being the result of latching an output of a variable frequency oscillator at the edge of the input reference pulse as information of phase error. CONSTITUTION:The reference pulse is inputted to an input terminal 1. A D flip-flop 2 latches an output data of the variable frequency oscillator 34 at the leading or trailing edge of the reference pulse. A prescribed value inputted from the input terminal 11 is subtracted from the output of the D flip-flop 2 at a subtraction circuit 3 and the result is supplied to a low pass filter 4 to control the variable frequency oscillator 34 comprising adder circuits 35, 36 and a delay circuit 38. The output of the variable frequency oscillator 34 controlled by the output of the low pass filter 4 is converted into a sinusoidal wave by a rom 39 and outputted at an output terminal 17.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a digital phase synchronization circuit used in digital televisions and the like, which generates digital data synchronized with a reference signal.

BACKGROUND ART In recent years, digitalization of signal processing has been actively carried out, and digital televisions and the like require a circuit that generates a digital signal synchronized with a reference signal, and demand for digital phase synchronization circuits is increasing.

A conventional digital phase synchronization circuit will be described below with reference to the drawings. Figure 3 is a block diagram showing the configuration of a conventional digital phase synchronization circuit, Figure 4 is a waveform diagram showing the output waveform of a variable frequency oscillator, and Figure 5 is a ROM diagram.
FIG. 3 is a characteristic diagram showing the input/output characteristics of (sequential output only memory).

In FIG. 3, the reference pulse signal inputted to the input terminal 30 is filtered by a low-pass filter 31 to remove high-frequency components and becomes a sine wave, which is multiplied by the output of the ROM 39 by the multiplier 32. The output of the multiplier 32 is filtered by a low-pass filter 33 and becomes a signal indicating the phase difference between the output of the low-pass filter 31 and the output of the ROM 2S, which controls a variable frequency oscillator 34 consisting of an adder circuit 35, an adder circuit 36, and a delay circuit 38. . Here, the operation of the variable frequency oscillator 34 will be explained using FIG. 4. The adder circuit 36 adds the output of the adder circuit 35 to the output of the delay circuit 38 (Z-' represents a unit delay, and a D flip-flop is used as a specific circuit, for example). Therefore, its output increases by the input of adder circuit 36 every clock. FIG. 4 is a diagram showing the change in the output of the adder circuit 36 over time, when the input of the adder circuit 36 is θ and the clock period is T. In FIG. 4, the horizontal axis represents time, and the vertical axis represents the output of the adder circuit 36, that is, the output phase of the variable frequency oscillator 34. As can be seen from FIG. 4, the output of the adder increases by θ every time T and returns to zero when the adder 36 overflows, repeating this operation. Therefore, the output of the variable frequency oscillator 34 becomes a step-like leakage wave whose frequency is proportional to θ, that is, the input of the adder circuit 36. By adding a constant value input from the input terminal 37 to the input of the variable frequency oscillator 34 in the adder circuit 35, the oscillation frequency can be controlled around a frequency corresponding to the constant value.

The oscillation output obtained in the above manner is a leakage wave as described above, and the phase cannot be compared by directly multiplying the output of the low-pass filter 31 with the reference sine wave obtained. The reference pulse signal is converted into a sine wave by the ROM 39 (in which the input/output characteristics of the sine wave are written as a table), which has a sine wave-like human output characteristic, is returned to the multiplier circuit 32, and is input to the input terminal 30. Obtain an output signal synchronized with This output is output to the output terminal 40.

Such an example is shown, for example, in Applications of Digital Signal Processing (Institute of Electronics and Communication Engineers) pp. 159-160.

Problems to be Solved by the Invention However, in the digital phase synchronization circuit configured as described above, it is difficult to synchronize the output with the edges of the reference pulse because the reference pulse is converted into a sine wave by a low-pass filter and the phases are compared. Furthermore, in the output of the low-pass filter 33, a frequency component of the sum of the output of the low-pass filter 31 and the output of the ROM 39 remains to some extent without being removed, and this component causes the output phase of the variable frequency oscillator 34 to fluctuate, causing a temporal phase error. arise. Furthermore, the multiplier used as a phase comparator has the disadvantage of being large in scale as a digital circuit.

SUMMARY OF THE INVENTION In view of the above problems, the present invention provides a digital phase synchronization circuit that generates an output signal that is precisely synchronized with the edge of a reference pulse and has no phase error by performing phase comparison without using a multiplier.

Means for Solving the Problems In order to solve the above problems, the digital phase synchronization circuit of the present invention includes a D flip-flop circuit that launches input data at the edge of a reference pulse, and subtracts a constant value from its output data. It includes a subtraction circuit, a low-pass filter that filters the output data of the subtraction circuit, and a variable frequency oscillator that oscillates at a frequency according to the output data, and the output data of the variable frequency oscillator is used as the input data of the D flip-flop circuit. It is configured to give as follows.

Effect of the Invention With the above-described configuration, the present invention can realize a digital phase synchronization circuit that generates an output signal that is accurately synchronized with the edge of a reference pulse and has no phase error.

Embodiment A digital phase synchronization circuit according to an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing the configuration of the digital phase synchronization circuit of the present invention, and the second
Figures (a) and +b+ are diagrams showing the output of the variable frequency oscillator and the reference pulse. In FIG. 1, a reference pulse is input to input terminal 1, and D flip-flop 2 latches the output data of variable frequency oscillator 34 at the rising or falling edge of the reference pulse. This embodiment will be described assuming that the signal is latched at the rising edge. The output of the D flip-flop 2 is subtracted by a constant value input from the input terminal 11 in a subtraction circuit 3, and then passed through a low-pass filter 4 to an addition circuit 3.
5 and 36, and a variable frequency oscillator 34 consisting of a delay circuit 38.
control. The variable frequency oscillator 34 is the same as that described in the conventional embodiment, so a description thereof will be omitted. Identical parts are given the same numbers.

Low-pass filter 4 includes coefficient circuits 8 and 9 and adder circuits 5 and 6.
, 10, and a delay circuit 7, which is a first-order digital filter having a proportional term. The input of the low-pass filter 4 is multiplied by A in the coefficient circuit 8, and added to the output of the delay circuit 7 in the adder circuit 5. The output of the adder circuit 5 is sent to a delay circuit 7 and an adder circuit 6, and the adder circuit 6 adds the output of the adder circuit 5 and the output of the delay circuit 7. The output of the adder circuit 6 is multiplied by eight in the coefficient circuit 9, and its output is added to the output of the coefficient circuit 8 in the adder circuit 10 and output as the output of the low-pass filter 4. The transfer function H(
Z) is expressed by the following equation (1).

Coefficients A and B are set according to the required response of the phase locked loop (PLL).

The output of the variable frequency oscillator 34 controlled by the output of the low-pass filter 4 is converted into a sine wave by the ROM 39 and output to the output terminal 17, while being sent to the data input of the D flip-flop 2. Note that if the output is only leakage, the ROM is not necessary. In this embodiment, the D flip-flop 2 and the subtraction circuit 3 function as a phase comparator, which will be explained below with reference to FIG.

FIG. 2(a) shows the output of the variable frequency oscillator 34 (bl indicates the reference pulse input to the input terminal 1). This is schematically shown as a straight line in this figure. In Figure 2 (a), D represents the value at which the adder 36 overflows. As can be seen from this figure, the variable frequency oscillator 34 For example, if the output of D is latched at the first edge of the reference pulse shown in (b), θ1 will be obtained as the output of the D flip-flop 2, and if it is latched at the next edge of the reference pulse, θ2 will be obtained. flip flop 2
A signal proportional to the phase difference between the reference pulse and the output of the variable frequency oscillator 34 is obtained at the output. Therefore, by subtracting the constant input from the input terminal 11 by the subtracter 3 from the output of the D flip-flop 2, an oscillation output synchronized with the edge of the reference pulse at an arbitrary phase can be obtained.

Effects of the Invention As described above, the present invention uses data obtained by latching the output of a variable frequency oscillator at the edges of the input reference pulse as phase error information, so that the output is accurately synchronized with the edges of the reference pulse and has no phase error. A digital phase-locked circuit that generates signals can be realized. Further, in the present invention, since a multiplier is not used in the phase comparator, a digital phase synchronization circuit with a small circuit scale can be realized.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a digital phase synchronization circuit in an embodiment of the present invention, FIG. 2 (al is a schematic diagram schematically showing the output waveform of a variable frequency oscillator, b) is a waveform diagram showing the reference pulse, Fig. 3 is a block diagram showing the configuration of a conventional digital phase synchronization circuit, and Fig. 4 is a waveform diagram showing the reference pulse.
The figure is a waveform diagram showing the output waveform of the variable frequency oscillator.
The figure is a characteristic diagram showing the input/output characteristics of a ROM (read only memory). 2...D flip-flop, 3...subtraction circuit, 4...low pass filter, 32...
. . . io path, 33 . . . low pass filter,
34...Variable frequency oscillator, 39...
ROM. Name of agent: Patent attorney Toshio Nakao and one other person Figure 2

Claims (3)

[Claims] (1) D to latch the input data at the edge of the reference pulse
The variable frequency oscillator includes a flip-flop circuit, a subtraction circuit that subtracts a fixed value from its output data, a low-pass filter that filters the output data of the subtraction circuit, and a variable frequency oscillator that oscillates at a frequency according to the output data. A digital phase locked circuit configured to provide output data of an oscillator as input data to the D flip-flop circuit. (2) The low-pass filter consists of a first coefficient circuit that multiplies input data by a constant, and a first coefficient circuit that delays data by a unit delay time.
a first addition circuit that adds the input data and output data of the first delay circuit and provides the output data as input data to the first delay circuit; and the first delay circuit. a second addition circuit that adds the output data of the first addition circuit to the output data of the first addition circuit; a second coefficient circuit that multiplies the output data of the second addition circuit by a constant; The digital phase synchronization circuit according to claim 1, further comprising a third addition circuit that adds the output data and the output data of the second coefficient circuit. (3) The variable frequency oscillator includes a fourth addition circuit that adds a constant value to input data, a second delay circuit that delays the data by a unit delay time, and a combination of the output data of the fourth addition circuit and the second The digital circuit according to claim 1, further comprising a fifth adding circuit that adds output data of the delay circuits and supplies the output data as input data to the second delay circuit. Phase-locked circuit.