JPH0435536A - Bit synchronizing circuit - Google Patents

Abstract

PURPOSE:To shorten the operation time of a circuit and to reduce power consumption by integrating outputs of a first and a second saw tooth wave generators by a first and a second integrators, applying an output voltage subtracted by a subtracting circuit to a voltage control delay element as a control voltage, varying its delay amount and executing the control so that output waveforms of both saw tooth wave generators become the same. CONSTITUTION:As for a first saw tooth wave generator 1, charging is started by a rise of input data and reset is applied by a fall of a system clock. As for a second saw tooth wave generator 2, charging is started by a fall of the system clock and reset is applied by a fall of the input data. A first and a second integrators 3, 4 integrate outputs of a first and a second saw tooth wave generators 1, 2, respectively, a subtracter 5 subtracts the output of a second integrator 4 from an output of a first integrator 3 and a voltage control delay element 6 controls a delay amount of a phase of the input data by setting an output voltage as a control voltage. A flip-flop 7 inputs the output of the voltage control delay element 6 and outputs an output for determining a timing for outputting the input data in accordance with the system clock. In such a way, the circuit operation time is shortened and the power consumption can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention is applied to a bit synchronization circuit in a digital signal receiving device.

〔overview〕

The present invention provides a bit synchronization circuit equipped with means for synchronizing input data and a system clock. A sawtooth wave generator is provided that starts charging when the input data falls and is reset when the input data falls, so that the output waveforms of these two sawtooth wave generators are equal.
The outputs of these sawtooth wave generators are replaced with analog signals to be used as control voltages for voltage-controlled delay elements, and the amount of delay is controlled to adjust the amount of phase delay of input data and/or system clock to achieve bit synchronization. This makes it possible to achieve bit synchronization using the same circuit even if the speed of human data differs, without having to design a dedicated circuit.

[Conventional technology]

Conventionally, this type of bit synchronization circuit has used a digital logic circuit as a circuit to increase or decrease the number of delay elements in the circuit in order to integrate the bit phase of input digital data (for example, in the US Institute of Electrical and Electronics Engineers, Journal Selected Areas Communication: IE[E
E Journal on 5elect-ed Ar
ease in Communications No.
, 8.1987.10).

Next, the operation will be briefly explained using FIG. 4.

First, the human data 21 is a delay element 8 with a certain delay value.
1-8. , the flip-flop 7° latches the data at a timing delayed by one delay element 9 due to the system clock 22, and latches the data at a timing delayed by two delay elements 91 and 92. Flip-flop 72 and delay element 9. ~9. ．． a flip-flop 7 that latches at a timing with a delay of n times;
and latches.

The selection signal for the delay value of the data line is first input to the input data 21.
The 0 bit rate and the length of the latch timing shift from flip-flop 71 to flip-flop 7° are made equal. Now, when the system clock 22 reaches the flip-flop 71 with a delay of one delay element 91, the phase of the input data 21 is higher than that of the delay elements 81 to 8. .

and if the phase is the same when it passes through the selector 10 and reaches the flip-flop 71, then the phase changes from the flip-flop 71 to the flip-flop 71. This means that the same data was latched in all cases.

However, if the phase of the input data 21 that reaches the data terminal of the flip-flop 7 is earlier than the system clock 22, the data phase will be earlier from the flip-flop 7h to the (n-1)th and (n-2)th data terminals. This makes it impossible to latch the same data. On the contrary, human power data 21
When the phase of the flip-flop becomes delayed, it becomes impossible to latch the same data as other flip-flops in order from flip-flop 7 by a delayed time.

In this way, by utilizing the fact that the number or position of flip-flops that can latch the same data changes depending on the phase difference between the input data 21 and the system clock 22, the output from the flip-flop 7 to the flip-flop 7h is A particular control signal 26 is produced by passing it through the majority logic circuit 11, the delay decision circuit 12 and the latch circuit 13.

And all the flip-flops 71-71. latches the same data, all flip-flops 71-7. , are in the same state), so as not to increase or decrease the number of data delay elements.
．． When the input data 210 phase is delayed (a state in which flip-flops with a lower number cannot latch), increase the number of delay elements. Controls the selector 10.

By repeating the operations described above, the phases of the system clock 22 and the input data 21 are always synchronized.

[Problem to be solved by the invention]

This conventional bit synchronization circuit requires that the bit rate of the input data be set to the same value as the delay value of the clock signal entering the flip-flop that latches the input data connected to the system clock. In other words, there was a problem in that a dedicated bit synchronization circuit had to be designed for each input data speed.

Furthermore, since the control method is digital, delicate synchronization cannot be achieved and it takes a long time to reach the synchronization end state, which causes the problem that the circuit operates for a long time and increases power consumption.

An object of the present invention is to provide a bit synchronization circuit that can easily achieve bit synchronization using the same circuit even if input data is different by solving the above-mentioned problems.

[Means to solve the problem]

The present invention provides a bit synchronization circuit equipped with a means for synchronizing input data and a system clock, including a first sawtooth wave generator that starts charging at the rising edge of input data and reset at the falling edge of the system clock; a second sawtooth wave generator that starts charging at the falling edge of the clock and resets at the falling edge of the input data;
first and second integrators that integrate the outputs of the first and second sawtooth generators, respectively; and a subtracter that subtracts the output of the second integrator from the output of the first integrator; A voltage-controlled delay element that controls the amount of phase delay of input data using the output voltage of this subtracter as a control voltage, and a timing to input the output of this voltage-controlled delay element and output the input data in accordance with the system clock. It is characterized by comprising a flip-flop that outputs an output.

The present invention also provides a bit synchronization circuit equipped with means for synchronizing input data and a system clock, including a first sawtooth wave generator that starts charging at the rising edge of the input data and is reset at the rising edge of the system clock;
a second sawtooth wave generator that starts charging at the falling edge of the system clock and resets at the falling edge of input data; and a first and second sawtooth wave generator that integrates the outputs of the first and second sawtooth wave generators, respectively. an integrator; a first voltage-controlled delay element that uses the output voltage of the first integrator as a control voltage to adjust a phase delay amount of input data; and a system that uses the output voltage of the second integrator as a control voltage. a second voltage-controlled delay element that adjusts the amount of phase delay of the clock; and an output of the first voltage-controlled delay element as input, and an output of the second voltage-controlled delay element as clock input;
It is characterized by comprising a flip-flop that outputs an output that determines timing.

[Effect]

The first sawtooth wave generator starts charging at the rising edge of input data and is reset at the rising edge of the system clock, and the second sawtooth wave generator starts charging at the falling edge of the system clock and resets at the falling edge of the input data. It takes a reset. Therefore, if the input data and the system clock are synchronized and the centers of their pulses coincide, the output waveforms of both sawtooth wave generators will be the same, but if they are out of synchronization, the output waveforms will be different. Become.

Therefore, the analog output voltage obtained by integrating the outputs of both sawtooth wave generators using the first and second integrators is applied to the voltage controlled delay element as a control voltage, and the amount of delay is changed. By controlling the output waveforms to be the same, it is possible to achieve phase synchronization between the human input data and the system clock.

That is, in the present invention, since a voltage-controlled delay element is used as a delay element and the phase difference detection component is replaced with an analog signal, the delay amount of the data line can be adjusted steplessly, and a dedicated circuit can be designed depending on the data speed. This makes it possible to eliminate the need to do so.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of the present invention.

The present embodiment is a bit synchronization circuit equipped with means for synchronizing input data and a system clock, and the feature of the present invention is that charging starts at the rising edge of the input data 21 and starts charging at the rising edge of the system clock 22. A first sawtooth wave generator 1 which is reset, a second sawtooth wave generator 2 which starts charging at the falling edge of the system clock 22 and is reset at the falling edge of the input data 21, and the first and second saws. first and second integrators 3 and 4 that integrate the outputs of the wave generators 1 and 2, respectively, and a subtractor 5 that subtracts the output of the second integrator 4 from the output of the first integrator 3;
Input data 2 is set using the output voltage of this subtracter 5 as a control voltage.
a voltage-controlled delay element 6 that controls the amount of phase delay of 1; and a flip-flop that receives the output of the voltage-controlled delay element 6 and outputs an output 25 that determines the timing of outputting the input data 21 in accordance with the system clock 22. 7.

Next, the operation of the present embodiment will be explained using the timing chart shown in FIG. In FIG. 2, output 23 represents the output of sawtooth wave generator 1, and output 24 represents the output of sawtooth wave generator 2.

Now, when the input data 21 and the system clock 22 are synchronized in phase (state of waveform 101 and waveform 103), the time t1 from the rise of waveform 101 to the rise of waveform 103, and the edge of waveform 103 are Assuming that the time t2 to the edge of waveform 101 is the same, waveform 1
06 and waveform 108 have the same shape.

In this case, when the integrated waveform 106 and waveform 108 are subtracted, the output of the subtracter 5 becomes zero. In other words, there is no voltage change component that controls the voltage-controlled delay element 6.

Next, if the phase of the input data 21 is delayed compared to when it is synchronized, (states of waveforms 102 and 105), there is a difference in the output waveforms 107 and 109 of the two sawtooth wave generators 1 and 2. occurs. That is, when two sawtooth waves are subtracted in integrated form, a voltage component with a positive value is produced.

This means that the voltage applied to the voltage-controlled delay element 6 is higher than when the input data 21 and the system clock 22 are synchronized, and the time required for the input data 21 to pass through the voltage-controlled delay element 6 is becomes shorter. As a result, the delayed phase is reduced.

Conversely, when the input data 21 is ahead in phase, the magnitudes of the saws of the outputs 23 and 24 are opposite to those when the input data 21 is delayed in phase. The output becomes negative, and the voltage level applied to the voltage controlled delay element 6 is lower than when the input data 21 and the system clock 22 are synchronized.
A phase of 1 will result in an increased delay.

As a result, the flip-flop 7 outputs an output 25 that determines the timing for outputting the input data 21 in accordance with the system clock 22.

FIG. 3 is a block diagram showing a second embodiment of the present invention.

In the second embodiment, the subtracter 5 is removed from the first embodiment shown in FIG. a first voltage-controlled delay element 6a that adjusts the delay amount of the system clock; a second voltage-controlled delay element 6b that adjusts the phase delay amount of the system clock using the output voltage of the second integrator 4 as a control voltage; A flip-flop 7 which uses the output of the first voltage-controlled delay element 6a as a human input and the output of the second voltage-controlled delay element 6b as a clock input, outputs an output that determines the timing of outputting input data in accordance with the system clock. It is prepared.

In the second embodiment, the two sawtooth waves output as phase difference components are not subtracted after being integrated, and the voltage-controlled delay elements 6a and 6b are connected to the two signals, respectively. On the other hand, the phase of the system clock 22 is controlled. With this,
An advantage is obtained that the delay until synchronization can be greatly reduced.

〔Effect of the invention〕

As explained above, the present invention uses a voltage-controlled delay circuit for the data line delay and replaces the phase difference detection component with an analog signal, so the amount of data line delay can be adjusted steplessly, and the data line delay can be adjusted steplessly. Depending on the speed, there is no need to design a dedicated circuit.

Furthermore, the delay until synchronization can be greatly reduced, and the opening time of the circuit during operation can be shortened.

Furthermore, if the feedback capacitor of the operational amplifier used in the sawtooth wave generator and the capacitor and resistor used in the integrator are removed, the circuit can be made smaller than the conventional bit synchronous circuit.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a first embodiment of the present invention. FIG. 2 is a time chart showing the operation. FIG. 3 is a block diagram showing a second embodiment of the present invention. FIG. 4 is a block diagram showing a conventional example. 1.2... Sawtooth wave generator, 3.4... Integrator,
5... Subtractor, 6.6a, 6b... Voltage controlled delay element, 7.71-7. , ... flip-flop, 8. ~
8. ．． ．． 91-9...Delay element, 10...Selector, 11...Majority logic circuit, 12...Delay determination circuit, 13...Latch circuit, 21...Input data, 2
2...System clock, 23.24.25...Output, 101-109...Waveform.

Claims (1)

[Claims] 1. In a bit synchronization circuit equipped with means for synchronizing input data and a system clock, a first sawtooth wave is generated that starts charging at the rising edge of the input data and resets at the falling edge of the system clock. a second sawtooth wave generator that starts charging at the falling edge of the system clock and resets at the falling edge of the input data; and first and second sawtooth wave generators that integrate the outputs of the first and second sawtooth generators, respectively. a second integrator, a subtracter that subtracts the output of the second integrator from the output of the first integrator, and the amount of phase delay of input data is controlled using the output voltage of the subtracter as a control voltage. A bit synchronization circuit comprising a voltage-controlled delay element. 2. In a bit synchronization circuit equipped with means for synchronizing input data and a system clock, there is a first sawtooth wave generator that starts charging at the rising edge of input data and is reset at the rising edge of the system clock; a second sawtooth wave generator that starts charging at the downstream and resets at the falling edge of the input data; first and second integrators that integrate the outputs of the first and second sawtooth generators, respectively; a first voltage-controlled delay element that uses the output voltage of the first integrator as a control voltage to adjust the amount of phase delay of input data; and uses the output voltage of the second integrator as a control voltage to adjust the phase delay of the system clock. a second voltage-controlled delay element that adjusts the amount of delay; the output of the first voltage-controlled delay element is used as an input, the output of the second voltage-controlled delay element is used as a clock input, and an output that determines timing is outputted. A bit synchronization circuit characterized by comprising a flip-flop.