JPS633543A - Serial transfer equipment - Google Patents

Abstract

PURPOSE:To attain the diagnosis of a serial transfer equipment by receiving sent data while being fed back and comparing the received data with data before transmission. CONSTITUTION:A parallel data written in a shift register 7 from a central processing unit (CPU) 1 and the data sent to a transmission line 18 from an output section 19 of the shift register 7 by using a clock signal from a clock generator 15. The signal of the line 18 is inverted via a feedback path 11 and inputted to an input section 20 of the shift register 7. The CPU 1 reads the parallel data from the shift register 1 aud compares it with test data at the time of the end of serial transmission.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a digital signal serial transfer device, and in particular, a circuit that returns and receives transmitted data and compares the returned data with the data before transmission. This invention relates to a circuit for diagnosing a serial transfer device.

[Conventional technology]

The self-diagnosis function of conventional serial transfer equipment is based on Motorola Semiconductors Advanced Information.
M.C. 686811 November 1983 pp. 3-4
Chapter 3.3.2 Local loopback mode and Chapter 4-1
Page 0 4/2/2/1 Channel Knee Mode Select (MOTROLA SEMICONDUCTOR3
Advance Information MC686
810CTOBER1983 PP3-43・3・2
LOCAL-LOOPBACK MODE, PP4-
104.4.2 C) IANNEL A MODE 5
ELECT). This serial transfer device converts parallel data written from a central processing unit (hereinafter referred to as CPU) into serial data using a shift register.
It has the function of serially transmitting data to the other station, converting the serial data sent from the other station into parallel data using a shift register, and transmitting it to the CPU.
It has a structure in which it has separate shift registers for transmission and reception so that transmission and reception can be performed using independent synchronization signals. In order to diagnose whether this serial transfer device operates normally, the transmission layer shift register converts test data written from the CPU etc. into serial data, and the return circuit causes the reception shift register to receive the data. It is possible for the CPU to read the returned data and compare it with test data.

However, in a serial transfer device that uses one shift register for transmission and reception, the conventional diagnostic method that self-returns the transmitted data and compares and verifies it is not suitable for transmitting, self-returning, and Since operations such as reception are not performed, the test data written by the CPU and the read data are the same, and cannot be distinguished from the results of normal operation, resulting in a problem that abnormalities cannot be detected.

[Problem that the invention seeks to solve]

The above conventional technology, as a device for diagnosing the function of a serial transfer device in which one shift register serves as both transmission and reception, does not take into consideration the detection of an abnormal state in which the shift function of the shift register is impaired. There was a problem in that it was not possible to distinguish between an occurrence and a normal situation.

An object of the present invention is to provide a diagnostic circuit for a serial transfer device using a shift register that serves both as a transmitter and a receiver.

[Means for solving problems]

The above purpose is to write test data into a serial transfer device, convert it to serial data, and transmit it.

This is achieved by providing an inverter in the self-circulating circuit that connects the transmitting path and the receiving path, which allows the data to be read after being received and compared with the written test data.

[Effect]

The diagnostic circuit of the serial transfer device according to the present invention serially transmits the written test data, receives the data by inverting its logic by half, and then operates so as to read the data. As a result, even if the shift function of the shift register that makes up the serial transfer device is impaired, the data that is read compared with the written test data is not logically inverted because it is not received through the inverter. The data becomes clear, and it becomes possible to distinguish between abnormal times and normal times.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

In the figure, the CPU that controls the human output of calculations and data
There is a control bus 2 for controlling peripheral devices and the like from the CPU, an address bus 3 for the CPU to distinguish between a plurality of peripheral devices and storage resources, and a data bus 4 for transmitting data. The serial transfer device 17 has an address bus 3 so that the CPU can write transmission data and read received data to the serial transfer device 17 via these buses.
Address a specific bit pattern connected with mother &! 3
There is an address decoder 5 that outputs a selection signal when indicated by , and it is possible to write and read parallel data by receiving a shift register selection signal 8 from the address decoder 5 and a write/output signal 6 from the control bus 2. A shift register 7 is connected to the data bus 4. A transmission path 18 is connected to the serial output section 19 of the shift register 7 for transmitting serial data to the opposite station 16. This transmission path 18
A return path 11 is connected to enable functional diagnosis of the serial transfer device 17, and the return path 11 is provided with an inverter 12 for logically inverting the serial data.

A data selector 10 is connected to the return path 11 and the reception path 13 that transmits serial data sent from the opposite station 16, and during normal transmission and reception, the serial data on the reception path 13 is transferred to the function of the serial transfer device 17. When making a diagnosis, data on the return path 11 is selected and transmitted to the shift register 7. Further, a data selector selection signal 8 and a data bus 4 are connected to the data selector 10 so that switching between normal transmission/reception and diagnosis can be performed by indicating a specific address and data by the CPU 1. . A clock generator 15 is provided so that the serial boot transmitted from the data selector 10 to the shift register input section 20 and the serial data from the shift register output section 19 are input/output by the shift register 7 in synchronization, and its output signal is The clock signal that is! 14 has a circuit configuration connected to the shift register 7 and the partner station 16.

The shift register 7 in FIG. 1 stores the parallel data written by C:PUl, and the shift register output section 19 outputs the data of the least significant bit of the shift register 7. Furthermore, when a clock signal is input, the shift register 20 shifts from the most significant bit to the least significant bit, and when shifting, the data in the shift register input section 20 is stored in the most significant bit. The clock generator 15 that inputs the clock signal 14 to the shift register 7 is
Clock signals are output for the number of bits of parallel data written to the shift register 7, and the clock signal is automatically generated by the CPU after the parallel data is written to the shift register 7. When the CPU 1 diagnoses the serial transfer device 17, the CPIJI sets the data selector 10 to select data on the return path 11, and writes test data into the shift register 7. By doing so, the clock generator 15 outputs a clock to the shift register 7, and the shift register starts serial transfer in synchronization with the clock signal. Serial transfer data is return route 1
1, and after being logically inverted by the inverter 12, it is returned to the shift register input section via the data selector 10. Therefore, if the CPU reads the data from the shift register 7 when the serial transfer is completed, Obtain data that is the logical inversion of the test data when written. However, if there is an abnormality such as a failure in the function of the shift register 7 to write or read data from the CPUI or the number of clock signals generated by the clock generator 15 is different from the number of parallel data, after the transfer is completed, Since the data read from the shift register 7 is different from the logically inverted version of the test data at the time of writing, the serial transfer device! ! 17 abnormalities in CPU
It can be detected by I.

According to this embodiment, since the inverter 12 is used in the return path, the data written by the CPU, which may occur due to a failure of the shift function of the shift register 7 or disconnection of the clock signal line 14, is actually serially transferred. Regarding abnormalities that were not present,
Since the test data written to the shift register 7 and the data read out are the same and the logic is not inverted, there is an effect that an abnormality can be detected.

〔Effect of the invention〕

According to the present invention, it is possible to distinguish between a malfunction and a normal shift function of a serial transfer device constituted by a shift register that also serves as transmitter and receiver, and the above-mentioned abnormality can be detected6.

[Brief explanation of drawings]

The figure is a block diagram showing one embodiment of the present invention. 1... CPtJ, 2... Control bus, 3... Address bus, 4... Data bus, 5... Address decoder, 6... Write/read signal, 7... Shift register, 8... Shift register selection signal, 9... Data selector selection signal, 1o... Data selector, 11
... return path, 12 ... inverter, 13 ... reception path,
14... Clock signal line, 15... Clock generator, 16... Partner station, 17... Serial transfer device,
18... Transmission path, 19... Series output section, 20...
Series input section.

Claims (1)

[Claims] 1. A shift register that converts multiple bits of parallel data into serial data and outputs it, inputs the serial data and converts it into parallel data, a transmission line that transmits the serial data output of the shift register, and a transmission line that transmits the received data. and the receiving path that comes from
A return path for inputting the signal of the transmission path into the shift register and converting it into parallel data, and selecting whether to input either the signal of the return path or the signal of the reception path to the shift register. 1. A serial transfer device comprising a data selector and a clock generator for controlling a serial-to-parallel conversion operation of the shift register, characterized in that an inverter is provided in the return path.