JPS6336030B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to a vector data processing device for processing vector data provided in a vector computer.

(2) Background of the technology In recent years, pipeline control methods have rapidly developed in order to make effective use of computers, but this method also requires a large amount of hardware and is difficult to use efficiently. Improvements were requested in terms of usage.

(3) Prior art and problems In vector computers, etc., in order to perform vector operations, a large amount of vector data is transferred from the main memory to a vector register, etc., and the data is sequentially read out from the vector register and processed by the arithmetic unit. The calculation is performed and the obtained data is written into a vector register, and the data written into the vector register is transferred to the main memory and written. These are generally executed in three stages: a load instruction, an arithmetic instruction, and a store instruction, but one store pipeline is required to execute a store instruction that writes from a vector register to main memory.
In conventional vector operations, two load pipelines are required exclusively for this purpose, and two load pipelines are required exclusively for executing a load instruction to write from the main memory to a vector register. Therefore, a store access pipeline control section and a load access pipeline control section are provided independently to control each pipeline, and as shown in FIG. Each load pipeline has a data buffer section and an align section. On the other hand, regarding data buffers, vector registers or mask registers are generally connected not only to an access pipeline but also to multiple operation pipelines, in order to perform continuous pipeline processing such as load, operation, and store. requires a configuration that allows multiple pipelines to access vector registers independently, and for this purpose conventionally the vector registers are interleaved and the timing at which each pipeline uses the vector register is specified. ing. In this case, the timing of writing to or reading from the vector register and the timing of data exchange with the main memory are independent, so using a data buffer, the timing of accessing the vector register depends on the timing of data exchange with the main memory. This was done in such a way that it would not happen. However, having a data buffer section and an align section in each access pipeline increases the amount of hardware, which poses a problem in terms of efficient utilization.

(4) Purpose of the Invention In view of the above-mentioned problems, the present invention is based on the idea of sharing the data buffer section and align section of each of the store pipeline and the load pipeline, and by sharing the pipelines. It is an object of the present invention to provide a vector data processing device that can improve the processing speed of vector data with a relatively small amount of hardware.

(5) Structure of the Invention According to the present invention, the main memory and vector register in which pipeline processing is executed, and data read from the vector register and data read from the main memory are selectively written. A vector register/main memory in which data written to the main memory in response to a store instruction and data written to the vector register in response to a load instruction can be selectively read. This is achieved by providing a vector data processing device having a data buffer for holding data during transfer.

(6) Embodiment of the Invention FIG. 2 is a block diagram showing an embodiment of a vector data processing device according to the present invention. In FIG. 2, the vector data processing device according to the present invention includes a vector register 11 consisting of one or more elements, a main memory 12, reading data from the main memory 12 and writing to the vector register 11, and An access pipeline 13 that sequentially reads from the register 11 and writes it to the main memory 12; an instruction control unit 15 that issues a switching instruction between a store instruction and a load instruction of the access pipeline 13; It also includes a main memory processing section 14 that performs processing.

Further, the access pipeline 13 includes an address generation section 131 that generates a request address, an alignment processing section 133 composed of a data buffer and an alignment section, and an access pipeline control section 132. On the other hand, the main memory processing section 14 includes a main memory access control section 141 that performs activation of the main memory 12, etc., and a main memory data processing section 142 that performs error correction and the like.

FIG. 3 is a block diagram showing in more detail the structure of the alignment processing section 133 used in the present invention. In FIG. 3, the alignment processing unit 133
The data buffer DB is composed of a data buffer DB, an align section AL, and select circuits SL1 and SL2, and FIG. 4 is a block diagram showing the structure of the data buffer DB in more detail.

In such a configuration, the function of the vector load instruction is to transfer vector data from the main memory 12 to the vector register 11 or mask register. and the vector length in advance, and then create a request address by sequentially adding distance to the start address, and transfer from the main memory 12 to the vector register 11 or mask register by the number of elements indicated by the vector length. This is done by On the other hand, the function of the vector store instruction is to transfer data from the vector register 11 or mask register to the main memory 12, and in this case, it is performed in the same manner as described above.

Based on the requested address issued by the address generation unit 131, the main memory access control unit 141
A priority is set for accessing the CPU or CHP (not shown), etc., and a data request (store instruction) or data sending (load instruction) signal is sent to the main memory 12 activation and access pipeline 13. Controls the exchange of data such as
The main memory data processing unit 142 also receives store data from the alignment processing unit 133, creates data and check bits for the main memory 12, and processes read data from the main memory 12.
Error correction is performed using ECC (error correction code).
In the align processing unit 133, while the main memory data processing unit 142 corresponds to a request address by bus, it corresponds to a data buffer, vector register, or element order, so it is necessary to convert between element correspondence and address correspondence. contains an align section to align the data.

Switching between the store pipeline and the load pipeline is performed in the access pipeline 13. The alignment processing section 133 of the access pipeline 13 has the configuration shown in FIG. 3, as described above. In the case of a store instruction, the flow of write data from the vector register 11 to the main memory data processing unit 142 is as follows: vector element VE1 → line _L1 → select circuit SL2 → data buffer DB
→ Line L ₂ → Select circuit SL1 → Align section AL
→ Line L ₃ → Data element DE → Main memory data processing section 142. On the other hand, in the case of a load instruction, the flow of write data from the main memory data processing unit 142 to the vector register 11 is as follows:
Main memory data processing section 142 → Line L ₄ → Select circuit SL1 → Align section AL → Align element AE → Select circuit SL2 → Data buffer
It is transferred as DB→vector element VE2.

In such data transfer, the store/load switching of the select circuits SL1 and SL2 is performed as follows. That is, the instruction control unit 15 supplies a start and an operation code to the access pipeline control unit 132, and at the same time, a start signal for a pipeline such as an operation is supplied to an arithmetic unit (not shown). Load/store control of the access pipeline control unit 132 is performed by the start signal, and the operation code is decoded by the access pipeline control unit 132, and a switching signal is generated depending on whether the operation code is a load instruction or a store instruction. is the select circuit of the align processing section 133
It is sent to SL1 and SL2, and store/load gate switching is performed. In this case, the operation code is held in the control unit 132 until the store or load is completed.

(7) Effects of the Invention As explained in detail above, the vector data processing device according to the present invention shares the data buffer and align section of the load and store pipelines, so it is possible to process vector data with a relatively small amount of hardware. Processing speed can be improved.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an alignment processing section of a conventional vector data processing device, FIG. 2 is a block diagram showing the configuration of a vector data processing device according to the present invention, and FIG. FIG. 4 is a block diagram showing the processing section in detail, and a diagram showing a data buffer of the alignment processing section shown in FIG. 3. (Explanation of symbols), 11...vector register,
12...Main memory, 13...Access pipeline, 14...Main memory processing section, 15...Instruction control section, 131...Address generation section, 132...Access pipeline control section, 133...Align processing section , 141...main memory access control unit, 14
2...Main memory data processing section, SL1, SL2...
Select circuit, DB...data buffer, AL...
...Align section, VE1, VE2...Vector element, ARB...Align register buffer,
ALB...Align bus.

Claims (1)

[Scope of Claims] 1. A vector data processing device that processes vector data using an access pipeline provided between a vector register and a main memory, wherein the access pipeline processes a starting address, a distance, and a vector. an address generating unit 131 that generates a request address by setting a length in advance and sequentially adding distance to the first address; and an access unit that controls storing to the main memory and loading to the vector register based on a start signal and an operation code. A pipeline control unit 132, a data buffer DB that holds access data to the main memory, an align unit AL that converts between element correspondence and address correspondence, and an input side of the data buffer and an output side of the align unit. a second select circuit SL2 provided between;
an alignment processing section 133 having the main memory and a first select circuit SL1 provided on the output side of the alignment section, and the operation code decoded by the access pipeline control section is a load instruction or a store instruction. The select circuits SL1 and SL2 are switched by a switching signal issued according to whether
and the data buffer and the first select circuit.
Data is transferred to the main memory via SL1 and the align section, and when a load command is issued to the vector register, data is transferred from the first select circuit to the vector register via the align section, the second select circuit, and the data buffer. A vector data processing device characterized in that it transfers data.