JPS6336536B2 - - Google Patents

Description

Detailed Description of the Invention (a) Technical Field of the Invention The present invention relates to a central processing unit (CPU) having a main storage unit (MSU) and a store-through type buffer memory (BS), It relates to a buffer memory coincidence control method in a data processing system consisting of a plurality of other processing devices including a vector unit (VU) that performs memory access of The present invention relates to a control method for the second tag unit in a system having a tag unit.

(b) Technical Background FIG. 1 is a block diagram schematically showing an example of the configuration of a data processing system to which the present invention is applied. and channel processor (CHP) 5
and N pieces (N
It consists of a memory control unit M (MCU) 2 having M (M = 4) memory address ports including = 2), and simultaneously handles at least N address ports of a vector unit (VU) 4 in one memory cycle. Other devices that can be accessed {channel processor (CHP) 5, central processing unit (CPU) 3, etc.}
shows a data processing system that can perform one memory access in one memory cycle.

In the data processing system, a store-through type buffer memory (BS) {consisting of a tag section (hereinafter referred to as TAG1) 6 and a data section} is provided in a central processing unit (hereinafter referred to as CPU) 3.
As a method for efficiently matching the contents of the main storage unit (MSU) 1 and the main storage unit (MSU) 1, a separate tag unit (hereinafter referred to as TAG2) is provided in the memory control unit (MCU) 2.
7 from the vector unit (VU) 4 above.
For example, a vector unit (hereinafter referred to as
When a store access is made from main storage unit (MSU) 1 (called VU) 4, the store address and
A known method is known in which the store address is sent to TAG1(6) and invalidated only when the registered address of TAG2 matches.

Buffer memory (BS) using the above store-through method
In the case of fetch from CPU3,
When the fetch address and the address in TAG1(6) match, the contents of the data section of the buffer memory (BS) are used; if they do not match, the data is transferred from the main storage unit (MSU) 1 to the buffer memory (BS). Move it into the data section of the file and use that data. In addition, in the case of a store, the store address and
When the address in TAG1(6) matches, it is written to the data section of the buffer memory (BS) and is also written to main storage unit (MSU) 1 at the same time. )
Write only to 1.

In addition, in the case of a store from a device other than the above CPU 3, if the store addresses match,
Sends the store address to CPU3 as an invalidation (BI) address, and if it matches in CPU3, deletes the address from TAG1(6),
If there is a mismatch, the store address is discarded. In the case of a fetch, nothing is done because it does not affect the contents of the main storage unit (MSU) 1.

The principle of this coincidence control will be explained below.

First, the CPU 3 has the above-mentioned store-through type buffer memory (BS), and the channel processor (hereinafter referred to as CHP) 5 and VU 4 do not have the buffer memory (BS), but directly use the main storage unit (MSU) 1. access.

When loading data from main storage unit (MSU) 1, CPU 3 loads the buffer memory (BS).
Check TAG1(6), and if the required data block is not registered, main storage unit (MSU 1)
More block fetch {Buffer memory (BS)
registration unit data, here 64 bytes},
The data is used at the same time as it is registered in the data section of the buffer memory (BS). If the required data is already registered, it is loaded from the buffer memory (BS).

When the CHP 5 and VU 4 store to the main storage unit (MSU) 1, they directly store to the main storage unit (MSU) 1. If the CPU 3 had registered this storage address in the buffer memory (BS), a data mismatch would occur between the main storage unit (MSU) 1 and the buffer memory (BS).

The process of matching the data in the buffer memory (BS) with the data in the main storage unit (MSU) 1 at this time is the buffer invalidation (BI) process attempted to be performed in the present invention.

As the name suggests, the buffer invalidation (BI) process sends the store address used by CHP5 and VU4 to the above TAG1(6) of CPU3 and checks it. If they match, the corresponding TAG1(6) is The store address is deleted and invalidated, and if there is no match, the store address is discarded.

Therefore, if there is a match, the corresponding address will be erased from the buffer memory and it will be used again.
Even if data is loaded from the CPU 3, there is no corresponding data in the buffer memory (BS), so the aforementioned block fetch is performed on the main storage unit (MSU) 1, and as a result, the main storage unit (MSU) 1 and the contents of the buffer memory will match.

Next, the necessity of the above TAGs 2 and 7 will be explained. Generally, in a multiprocessor system or a system having a vector unit (VU) 4, data is stored in the main storage unit (MSU) 1 frequently.

For example, in the example shown in FIG. 1 above, there are two access pipelines (A access pipeline,
B access pipeline), two store accesses occur simultaneously.

On the other hand, the address check for invalidation (BI) processing in CPU3 uses a random access memory (RAM) element for the buffer memory (BS), so only one address can be checked in each cycle. .

Therefore, without the above TAG2(7), VU4 is originally capable of two store accesses every cycle, but due to CPU3 invalidation (BI) processing, only one store is stored every cycle. become unable to do so.

Also, when VU4 starts the store operation for CPU3,
Due to the above-mentioned invalidation (BI) processing, the performance of the CPU 2 must be significantly reduced.

In order to prevent such performance deterioration of CPU2 and VU4, the above-mentioned
Create an address buffer called TAG2(7). Since this TAG2(7) is an address buffer, there is no need for a data section like a buffer memory (BS).

This TAG2(7) is controlled to always have the address registered in the tag section TAG1(6) of the buffer memory (BS) in the CPU3.

That is, when the CPU 3 performs a block fetch, the address is always registered in the TAG2(7).

Specifically, when the CPU 3 loads data into the buffer memory (BS), if the same address is registered in the second tag section, the second
When all the ways in the second tag part have been registered, and the registered address and the registered address do not match, the oldest address in the second tag part is
Sends to the buffer memory (BS) of CPU3 and
At the same time as the CPU 3 performs the invalidation (BI) process for the address, the second tag section also performs the registration process for the load address.

Then, when CHP5 or VU4 stores, it is checked whether it matches the address registered in the TAG2(7), and only if it matches.
The address to be subjected to invalidation (BI) processing is sent to the CPU 3, and if they do not match, the address is immediately discarded.

In this way, without this TAG2(7), every time a store access is performed from the VU4 to the main storage unit (MSU) 1, an invalidation (BI) request regarding the address is sent to the buffer memory (BS). is issued, and the above buffer memory (BS) on CPU3
There was a problem that reduced the efficiency of use.

However, by providing TAG2(7) above, the corresponding
By making invalidation requests only for addresses that match in TAG2(7),
The usage efficiency of the buffer memory (BS) in the CPU 3 can be improved.

The present invention relates to a control method for this TAG2(7).

(c) Conventional technology and problems In the data processing system having the above TAG1(6) and TAG2(7), the conventional technology is as follows:
The same data was registered in TAG1 (6) and TAG2 (7), and the same data was deleted (invalidation processing).

Therefore, the main storage unit (MSU) 1 from the vector unit (VU) 4 of a supercomputer etc.
In a system where there are N address ports for TAG1(6) and memory access requests for the N address ports are issued simultaneously in one operation cycle, N pieces of hardware identical to TAG1(6) are required. Furthermore, due to the invalidated addresses from the N address ports, etc., there is a problem in that the amount of hardware required for a circuit for erasing the same address registered in TAG2(7) becomes enormous.

Furthermore, in order to erase the same address from TAG2(7) in one operation cycle using invalidated addresses from N address ports, etc., all M addresses including N from the vector unit (VU) 4 must be erased. It was necessary to simultaneously stop memory accesses from ports.

(d) Purpose of the Invention In view of the above-mentioned conventional drawbacks, the present invention provides a data processing system having N address ports etc. in which the above-mentioned simultaneous accesses to the main memory occur. By using the invalidation address, the amount of hardware required for the circuit to erase the same address registered in the N TAG2 etc. can be reduced, and memory access of all ports is required to erase the invalidation address from the TAG2. The purpose of this invention is to provide a method that does not stop the main storage device and the buffer memory and maintains the consistency control function between the main storage device and the buffer memory.

(e) Structure of the Invention According to the present invention, this object is: (1) A central processing unit having a main storage unit (MSU), a main memory control unit (MCU), and a store-through buffer memory (BS). (CPU) and
In a data processing system consisting of a plurality of other processing units including a vector unit (VU) that performs n memory accesses in one machine cycle, a tag part of the buffer memory (BS) has at least the same contents as the tag part of the buffer memory (BS). The central processing unit ( When the CPU) loads data into the buffer memory (BS), if the same address is registered in the second tag section, all the ways in the second tag section have been registered,
In addition, when the registered address and the registered address do not match, the oldest address in the second tag part is sent to the buffer memory (BS) of the central processing unit (CPU), and the central processing unit ( At the same time, the CPU) performs invalidation processing for the address, and at the same time, the second tag section also registers the load address, thereby erasing the oldest address.
When the other processing device performs store access to the main storage unit (MSU), the contents of the main storage unit (MSU) and the buffer memory (BS) are made to match. However, the store address is referenced in the second tag part, and if there is a match,
The buffer memory (BS) is sent to the buffer memory (BS) and the buffer memory (BS) is invalidated, and if they do not match, the store address is not sent to the buffer memory (BS) and the second buffer memory (BS) is invalidated. A method of controlling a registered address of a tag part so as not to stop memory access from other processing devices by not performing any invalidation processing regardless of whether the address matches or does not match.

(2) a central processing unit (CPU) having a main storage unit (MSU), a main memory control unit (MCU), and a store-through buffer memory (BS);
In a data processing system consisting of a plurality of other processing units including a vector unit (VU) that performs n memory accesses in one machine cycle, a tag part of the buffer memory (BS) has at least the same contents as the tag part of the buffer memory (BS). The central processing unit ( When the CPU) loads data into the buffer memory (BS), if the same address is registered in the second tag section, all the ways in the second tag section have been registered,
In addition, when the registered address and the registered address do not match, the oldest address in the second tag part is sent to the buffer memory (BS) of the central processing unit (CPU), and the central processing unit ( At the same time, the CPU) performs invalidation processing for the address, and at the same time, the second tag section also registers the load address, thereby erasing the oldest address.
When the other processing device performs store access to the main storage unit (MSU), the contents of the main storage unit (MSU) and the buffer memory (BS) are made to match. However, when the other processing device performs a store access to the main storage unit (MSU) and matches the second tag section with the store address, it sends the data to the buffer memory and stores it in the buffer memory. At the same time, the store address valid (SAV) for all addresses input to the second tag section and the registered address valid (BFAV) of the central processing unit (CPU) are invalidated. is "off", and only when the detection output of the means is "on", it is recognized that there is no access to the second tag part, and the second tag part is accessed by the above store address. , a method of controlling to perform invalidation processing of the second tag section.

This can be achieved by deleting the circuit for erasing the invalidated address registered in the second tag part, or by simply providing a few erasing circuits only under specific conditions. There is an advantage that the contents of the storage device and buffer memory can be matched.

(f) Embodiments of the Invention First, to summarize the gist of the present invention, M access ports including N address ports that simultaneously access a main storage unit (MSU) from a vector unit (VU); In a data processing system having a buffer memory (BS) in a central processing unit (CPU), and having a second tag part corresponding to the N address ports separately from a tag part of the buffer memory (BS), the second tag part corresponds to the N address ports. The registered capacity of the tag section is made larger than the registered capacity of the tag section of the buffer memory (BS), and store access is performed from each of the above address ports to the main memory, and a match is made in the second tag section. In this case, the buffer memory (BS) is processed to invalidate the address, and if they do not match, the store address is not sent to the buffer memory (BS) and the second tag part is invalidated. Regardless of whether the registered address matches or does not match, the registered address is not invalidated at all, or only when there is no access to the second tag part, a slight erasure circuit is added and invalidated. By controlling, the amount of hardware for erasing invalidated addresses in the second tag section is reduced,
Furthermore, it is intended to prevent memory accesses from all address ports from being stopped due to the invalidation process.

Embodiments of the present invention will be described in detail below with reference to the drawings.
The above-mentioned FIG. 1 is a block diagram showing an outline of a configuration example of a data processing system to which the present invention is applied, and FIG.
FIG. 3 is a block diagram showing one embodiment of the present invention and another embodiment together, and FIG.
FIG. 3 is a diagram showing an example of the structure of addresses of TAG1 and TAG2. In this embodiment, there are two address ports, A port and B port, to simplify the explanation.

In FIG. 1, as mentioned above, 1 is the main storage unit (MSU), 2 is the memory control unit (MCU), and 3 is the main storage unit (MSU).
CPU, 4 is VU, 5 is CHP, 6 is buffer memory (BS) tag part TAG1, 7 is second tag part
It is TAG2. And among the address ports, A
The port is accessed only by VU4, and the B port is accessed by VU4, CHP5, and CPU3.

The buffer memory (BS) shown here is a well-known set associative type buffer memory, so it can be read by accessing its tag part TAG1(6) with a lower block address (line address). By looking for a match with the higher-order address, the presence or absence of a data block registered at the line address is searched, and is controlled by the store-through method as described above.

FIG. 2 shows the configuration of TAG1(6) and TAG2(7). As is clear from this figure, TAG1(6) consists of 64 lines x 16 ways, and among the memory addresses (31 to 4 bits), the lower addresses 25 to 20
Bit (64 lines) as line address, 1
Access the address area of 64 bytes (00 _HEX to 3F _HEX ) by line. Therefore, the address area that can be registered with TAG1(6) is 64 byte area x 64
Line x 16 ways = 64 kilobytes (hereinafter referred to as KB) area.

Since TAG2(7) is an address buffer as described above, it consists only of a so-called tag section and does not have a data section.

In this example, the tag part is composed of 512 lines x 2 ways, and the lower address 23-15 bits (512 lines) of the memory address (31-4 bits) are used as the line address.
Access the address area of 256 bytes (00 _HEX to FF _HEX ) using a line. Therefore, the address area that can be registered with TAG2(7) is 256 byte area x 512 lines x 2 ways = 256KB area,
It has four times the registration capacity of TAG1(6).

The registered capacity of TAG1(6) and TAG2(7) mentioned here is
As is clear from the above, this indicates the total size of the registered area that can be indicated by a certain registered address.

The structure of the above address is shown in Figure 4, and TAG1(6), TAG2(7) shown in Figure 2
The meaning of each address bit becomes clearer by comparing it with the configuration example.

Also, TAG2(7) is configured by port (A port, B port) as described above, but A port, B port
Since they are accessed every cycle from the port, they each have the same configuration.

Originally, TAG1 (6) and TAG2 (7) should have the same configuration, but TAG2 (7) needs to have the same number of address ports as VU4, and generally has N vector accesses (in this example, 2 Since N TAG2(7) are accessed simultaneously, there is a problem in that the amount of hardware required is enormous.

For example, when considering TAG2(7) corresponding to one address port of the address ports (A port, B port) that are accessed simultaneously, if the number of ways is "16 ways", which is the same as TAG1(,6),
This requires eight times as many address registers and a verification circuit, and the number of terminals of the logic block associated with the TAG2(7) increases accordingly, making it unsuitable for the recent trend toward higher integration.

Therefore, in this example, the number of ways of TAG2(7) is set to 1/8, which is 2 ways, and the number of lines is 8.
By doubling the number of lines to 512, the number of registered addresses stored is the same as that of TAG1(6) (64 lines x 16 ways =
512 lines x 2 ways = 1024), and the registration area unit is set to 4 times the size of TAG1 (6) from 64 bytes to 256 bytes as described above.

Therefore, the effect of the present invention is to determine what advantages can be obtained by making the size of one line of TAG2(7) (256 bytes) larger than the size of one line of TAG1(6) (64 bytes). However, as mentioned above, the number of stored items is TAG2(7).
Since the number is the same as "1024" in TAG1(6), as a result, the registration area of TAG2(7) is four times the registration area of TAG1(6) (hereinafter, TAG2(7)>TAG1( In this state, when performing a block fetch from main storage unit (MSU) 1 to TAG1 (6) and registering the address of the corresponding block in TAG2 (7), In addition, how the invalidation (BI) process by replacement will turn out will be a measure of its effectiveness.

First, the basic operation of TAG2(7) will be explained using FIGS. 1 and 2.

A CPU block fetch [refers to a 64-byte block transfer from main storage unit (MSU) 1 that is fetched when there is no necessary data in buffer memory access from CPU 3] transfers the data from port B to TAG2(7). Register the CPU block fetch address.

When registering an address using the above CPU block fetch, both way 0 and way 1 that make up TAG2(7) have already been registered {that is, the valid bit (V) is "1"}, and the registered address If the address you are trying to register now does not match (that is, there is no space available), replace the oldest address from way 0 and way 1, and use TAG1( 6)
It is necessary to issue an invalidation request to.

VU4 or CHP5 is main storage unit (MSU) 1
When a store access is made to , the address is sent to TAG2(7) for each port and referenced.

If the store address matches the registered address of TAG2(7), a request is issued to TAG1(6) of the central processing unit (CPU) 3 to invalidate that address.

In this case, since TAG2(7) is controlled not to erase (invalidate) the registered address, there is no need to stop memory access from other devices due to the invalidation process.
This operation is the key point of the present invention.

If the store address does not match the registered address of TAG2(7), the above invalidation request (hereinafter referred to as BI
) will not be carried out. Therefore, as mentioned above,
Simultaneous store access by N access ports from VU4 is possible.

The following three types of BI exist for TAG2(7) to TAG1(6).

1 BI by replacing TAG2(7) by CPU block fetch. (This is called BI by replacement.) 2. BI for addresses registered in both TAG1(6) and TAG2(7). (This is called effective BI) 3 It is not registered in TAG1(6), but it is registered in TAG2(7).
BI for addresses registered in . (This is called invalid BI) Reasons for occurrence of the above three types of BI and TAG2(7)>
The change in the number of BIs due to setting TAG1(6) will be explained below.

1 BI by replacement.

"Reason for BI Occurrence" As mentioned above, when registering an address to TAG2(7) by block fetch from CPU3, both way 0 and way 1 are registered, and the address to be registered and the registered address are If there is a mismatch, this is a BI that occurs by evicting the oldest address of way 0 and way 1.

"BI number change by setting TAG2(7)>TAG1(6)" By setting TAG2(7)>TAG1(6), TAG1
The number of BIs for (6) will decrease.

As mentioned above, for the registration area, TAG2
Since it is configured so that (7)>TAG1(6),
When performing a block fetch on CPU3,
The registered address for TAG1(6) will match the address already registered for TAG2(7) in many cases, and the number of mismatched cases will decrease.
The number of BIs will decrease.

2 Valid BI (according to store access from VU4, CHP5).

"Reason for BI occurrence" BI occurs when VU4 or CHP5 performs a store access to main storage unit (MSU) 1 to the address registered in both TAG1(6) and TAG2(7). It is.

“BI count change due to setting TAG2(7)>TAG1(6)” Addresses registered in TAG2(7) include at least addresses registered in TAG1(6), so the valid The incidence of BI is the same regardless of the size of TAG2(7).

3 Invalid BI (due to store access from VU4, CHP5).

"Reason for BI occurrence" Not registered in TAG1(6) and TAG2(7)
VU4 is a BI generated when CHP5 performs a store access to main storage unit (MSU) 1 for the address registered in .

Therefore, in CPU3, even if the BI address is sent, it does not match the address registered in TAG1(6), so it only matches TAG2 due to the store access from the VU4, and the address is discarded. This is why it is called invalid BI.

"BI count change due to setting TAG2(7)>TAG1(6)" If TAG2(7) is increased, the number of addresses registered in TAG2(7) increases, so the registered address and VU4, CHP5 This increases the probability of matching the store address from , and the number of invalid BIs for TAG1(6) increases.

As is clear from the above description, implementing the present invention has the disadvantage that invalid BI occurs and system performance deteriorates; however, the system operation, that is, the contents of the main storage unit (MSU) There is no problem at all with the function of matching the contents of the data section of the buffer memory (BS).

By independently managing the memory area accessed by the VU 4 and the like and the memory area accessed by the CPU 3 by the operating system (OS), the above-mentioned deterioration in performance can be reduced.

That is, the memory area accessed by CPU3,
If you separate the memory area accessed by VU4 etc., the address registered in TAG2(7) is the CPU
3 block fetch address only.

Therefore, the address stored by VU4 etc. is
Since this does not match the address registered in TAG2(7), even if TAG2 is configured as in the present invention, there will be almost no deterioration in performance.

However, in reality, even if the CPU3 and VU4 areas are managed independently by the operating system (OS), 100% separation is difficult, but the performance degradation caused by this can be almost ignored. This is the extent that it can be done.

Next, one embodiment of the present invention will be described with reference to FIG.

As mentioned above, it is assumed that the VU4 is connected to the A port, and the VU4, CPU3, and CHP5 are connected to the B port.

Normally, the VU 4 performs multiple (two in this example) memory accesses, for example, to each bank, within the same machine cycle in order to improve memory access performance. However, since the CPU 3 and CHP 5 basically perform sequential processing, there is at most one access within the same machine cycle.

Based on these conditions, in this example,
VU4 is connected to A port and B port,
The reason why CPU3 and CHP5 are connected to the same port is because VU4 accesses two items in one machine cycle, so it is connected to A port and B port, and CHP5 and CPU3 have priority for memory. This is to simplify the control by performing the control within one port.

First, the address registration operation when the CPU 3 performs a block fetch will be described.

At this time, the block fetch address from the CPU 3 is held in the register BFAR79, and at the same time, it is also set in the register BBI1R,711.
Then, for example, the registration control circuit 91 sends an INH signal that prohibits registration to TAG2(7) for one cycle to the circuit in front of the B port (priority circuit in Figure 1), and then The access request to TAG2(7) is suppressed and the registration operation of the registered address held in the BFAR 79 is guaranteed.

In the next cycle, the above block fetch address is set in BBI2R721, and
Ways 0, 1, and 701 of this tag part are accessed by lower bits 23 to 15 of BBI1R711,
Registers BTRR0, 731, BTRR1, respectively
Read data is output to 741.

This register BTRR0, 731, BTRR1,
The contents of address 741 (address 4 to 14 bits) and bits 4 to 14 of register BBI2R721 are compared in match circuit C751, and match outputs M0 and M are respectively output.
Outputs 1.

These outputs M0, M1 and variable bits V0, V
1 is sent to the B-port control unit (B-CTL) 761, which performs the following control.

That is, when V0·V1=V and M0+M1=M, the operation of the B port control unit (B-CTL) 761 for each value of V and M is as follows.

Here, V0 and V1 are valid bits for way 0 and way 1 of TAG2(7).

Therefore, V0, V1=(0,0),(0,1),(1,
0), when registering the corresponding address in TAG2(7) by block fetch in CPU3, it indicates that there is "vacancy" in TAG2(7). ) does not need to be replaced.

However, if V0, V1 = (1, 1) and the registered address does not match the address registered in TAG2(7), it is necessary to perform replacement.

Therefore, to control the registration operation, logic is required to distinguish whether the valid bits of the two blocks are "on" or not. That is, V having the logic of V=V1.V2 is used.

On the other hand, the reason for setting M0+M1=M will be explained next.

In this embodiment, TAG2(7) has a two-way configuration, and the address match signals for way 0 and way 1 are M0 and M1, and since registration for each way always involves registering a different address, which This is because control is performed using a signal indicating that one of the ways matches, that is, a signal of M0+M1=M. Below, specific operations will be explained for each case.

[When V, M = 0, 0] Way with variable bits V0, V1 = 0 (however,
When V0=V1=0, register the address held in BFAR79 in way 0). in particular,
When it comes to the write timing to way 0 and 1,
Lower bits 23 to 15 of BFAR79 are set to lower bit positions of BBI1R711 through selector 821, ways 0 and 1 are accessed at that output address, and upper bits 4 to 14 of BFAR79 are registered. .

In Fig. 3, the arrow leading from way 0,701 to way 1,700 is the registration data of TAG2(7), that is, the registration data (valid bits, address 4 to 14 bits) held in the BFAR79 mentioned above. Showing the bus.

[When V, M=0, 1] The address held in the BFAR 79 is overwritten for the matched way (way with M=1). The writing method is performed in the same manner as described above.

[When V, M = 1, 0] In this case, as mentioned above, ways 0 and 1 of TAG2(7) are already registered, and the address you are trying to register now does not match the registered address. Therefore, the address of the oldest way is sent through the selector (SEL) 78 to the replacement
The registered address held in the BI queue 772 and the way BFAR 79 after the expulsion is written based on the instruction from the registration control circuit 91.

[When V, M = 1, 1] Overwrite the address held in the BFAR 79 for the matched way. The light procedure is the same as above.

Next, the case of store operation from VU4 and CHP5 will be explained.

In this case, the following description assumes that VU4 accesses the store from port A. Regarding the A port,
There can be no registration action. That is, the registration operation for TAG2(7) is to register the same address in TAG2(7) as the address registered in TAG1(6) when CPU3 performs a block fetch as described above. Regarding the port, since only VU4 is connected, a registration operation from the A port is impossible.

First, the store address from VU4 is ABI1R
Ways 0, 1, and 700 are accessed by the lower bits 23-15.

In the next cycle, the above store address is shifted and set to ABI2R 720, and ATRR0 730 and ATRR1 740 have
The output of ways 0, 1, 700 (address 4 to 14 bits) is set, and the output data and ABI2R
The upper 4 to 14 bits of 720 are the match circuit C75.
0 and if a matching output is obtained, the ABI
The contents of 2R720 are the A port control unit (A-
Under the control of CTL 760, the BI request is input to the A port BI queue 770 and sent to the CPU 3.

When the VU 4 or CHP 5 performs store access from the B port, it operates in exactly the same way, the contents of the RBI2R 721 are input to the B port BI queue 771, and a BI request is made to the CPU 3.

However, in the present invention, the BI address registered in ways 0, 1, 700 of TAG2(7) is controlled so as not to be erased (i.e., invalidated) during store access from the above-mentioned VU4 etc. It is.

If a coincidence output is not obtained in the coincidence circuit C750, no BI request is made to the CPU 3, and the store address set in the ABI2R 720 is simply erased.

In addition, A port BI queue 770, B port BI queue 771, replacement BI queue 772
The BI address queued in is set in register BIR810 through selector 80,
The data are controlled to be sent to the CPU 3 in sequence.

In the store operation described in detail above, a store access is performed to the main storage unit (MSU) 1 from the A port or the B port, and the store address is assigned to each way for each port of TAG2 (7). The match circuit C750, 751 matches the address registered in either way, and if a match output is obtained, a BI request is sent to CPU3, but each way 700, 701 in TAG2(7) The unique feature is that it does not delete the store address registered in .

Another embodiment of the invention will be described with reference to the same FIG.

To summarize the features of other embodiments, the valid bits (store address valid (SAV) for each port, registration Only when all address valid addresses (BFAV) are off, invalid addresses registered in each way in TAG2(7) are deleted.

The hardware necessary to carry out the invention is
This is the TAG2 erase address register 811.

The BI address input to the A port BI queue 770 and the B port BI queue 771 includes a flag indicating ways 0 and 1 added from the A port control unit (A-CTL) 760 and a flag indicating that the BI is a store-based BI. (aforementioned SAV) and is sent to the CPU 3 through the selector 80, and at the same time, when the flag (SAV) indicating that it is a BI due to the store is "on", it is also sent to the erase address register 811 of the TAG2. is set and the next
Until the BI address is sent to CPU3, or
It is retained until it is deleted from TAG2(7).

Then, it is detected that the store address valid (SAV) from A port, B port, etc. and the registered address valid (BFAV) from B port are all off at the timing of accessing TAG2(7). When recognized by means (DET) 90, the applicable
Since TAG2(7) will not be accessed, the output of the TAG2 erase address register 811 will be
Select with selectors (SEL) 820 and 821,
Set to ABI1R710 and BBI1R711.

Then, in the next cycle, ABI1R71
Access each way using the lower bits 23 to 15 of 0, BBI1R711 as an address, turn off the valid bit (V) of the way indicated by the flag indicating way 0, 1, and turn off the valid bit (V) of the way indicated by the flag indicating way 0, 1. control to erase the store address of the way.

If the multiple valid bits for the BI address input from the A port and the B port (that is, SAV from the A port, and SAV and BFAV from the B port) are not all off, the TAG2 erase address register 811 is set. The address data that is displayed is held until the plurality of validators are turned off.

While the above is being held, if the next BI address is sent from port A or B to the TAG2 erase address register 811, the address held until then is erased and the next BI address is sent to the TAG2 erase address register 811. The new BI address that has been received is controlled to be set in the TAG2 erase address register 811.

Therefore, in this method, the multiple valid bits (SAV from A port, SAV, BFAV from B port) for the address sent from A port or B port are processed at the timing when TAG2(7) is accessed. When it's off,
Recognizing that there is no access to TAG2(7),
Since the BI address held in the TAG2 erase address register 811 is controlled to be erased, if it cannot be erased, it will not exist in TAG1(6) and will remain in TAG2(7) (i.e. ,invalid
BI), but as mentioned above, there is no problem at all with system operation, and as mentioned above, depending on the operating system (OS) management method,
It will hardly be a problem.

Furthermore, since the BI address from the replacement BI queue is an address that is not related to the invalidation process in TAG2(7) (i.e., registered address),
It is controlled so that it is not set in the TAG2 erase address register 811.

(g) Effects of the Invention As explained above in detail, the buffer memory coincidence control method of the present invention allows M accesses, including N address ports, to be simultaneously accessed from the vector unit VU to the main storage unit MSU. Buffer memory for ports and central processing unit CPU
In a data processing system that has a BS and has a second tag section corresponding to the N address ports in addition to the tag section of the buffer memory BS, the registered capacity of the second tag section is set to the tag section of the buffer memory BS. If a store access is made to the main memory from each of the address ports mentioned above and a match is found in the second tag part, the address is invalidated to the buffer memory BS. If there is no match, the store address is not sent to the buffer memory BS, and the registered address of the second tag part is set to the address regardless of whether it matches or does not match.
Only when no invalidation processing is performed or when there is no access to the second tag part, a certain amount of erasing circuitry is added and the invalidation processing is controlled to be performed. This has the advantage that not only can hardware be reduced, but it is not necessary to stop memory access from all ports in order to erase the same address from the second tag part in one machine cycle.

[Brief explanation of the drawing]

FIG. 1 is a block diagram schematically showing an example of the configuration of a data processing system to which the present invention is applied, FIG. 2 is a diagram showing an example of the configuration of a tag unit of a buffer memory and a second tag unit, and FIG. 4 is a diagram showing one embodiment of the present invention and other embodiments together as a block diagram.
The figure shows an example of the structure of addresses for TAG1 and TAG2. In the drawings, 1 is a main storage unit (MSU), 2 is a memory control unit or main memory control unit (MCU), 3 is a central processing unit (CPU), 4 is a vector unit (VU), and 5 is a channel processor. (CHP), 6
is the tag part TAG1 of the buffer memory, 7 is the second tag part TAG2, 700, 701 are each way of the second tag part, 750, 751 are the matching circuits C, 770,
771 and 772 are buffer memory invalidation address queues, 810 is a buffer invalidation address register (BIR) for the central processing unit, and 811 is a second buffer memory invalidation address queue.
90 is a means (DET) for detecting that the store address valid (SAV) from each port and the registered address valid (BFAV) from the central processing unit (CPU) are "off". , 91 indicate registration control circuits, respectively.

Claims (1)

[Claims] 1. A main storage unit (MSU), a main memory control unit (MCU), a central processing unit (CPU) having a store-through type buffer memory (BS), and n memories in one machine cycle. In a data processing system consisting of a plurality of other processing devices including a vector unit (VU) that performs access, a second tag section that holds at least the same content as the tag section of the buffer memory (BS) is used as the main tag section. The memory control unit (MCU) is provided with n pieces, the registered capacity of the second tag part is larger than the registered capacity of the tag part of the buffer memory (BS), and the central processing unit (CPU) is configured to control the buffer memory (BS). When loading data to, if the same address is registered in the second tag part, all the ways in the second tag part have been registered, and the registered address and the registered address do not match. Sometimes, the oldest address of the second tag part is sent to the buffer memory BS of the central processing unit (CPU), and at the same time as the central processing unit (CPU) invalidates the address, In the second tag unit, the oldest address is erased by performing the registration process of the load address, thereby invalidating the second tag unit, and the other processing device is When performing a store access to the storage device (MSU), the store address is referenced in the second tag section to match the contents of the main storage device (MSU) and the buffer memory (BS). , if they match, the store address is sent to the buffer memory (BS) and the buffer memory (BS) is invalidated; if they do not match, the store address is not sent to the buffer memory (BS). , and controls the registered address of the second tag part so as not to stop memory access from other processing devices by not performing any invalidation processing regardless of whether the address matches or does not match the above. A buffer memory coincidence control method characterized by the following. 2. A central processing unit (CPU) that has a main storage unit (MSU), a main memory control unit (MCU), a store-through type buffer memory (BS), and a vector unit (which performs n memory accesses in one machine cycle). In a data processing system consisting of a plurality of other processing units including a buffer memory (BS), a second tag unit holding at least the same content as the tag unit of the buffer memory (BS) is connected to the main memory control unit (MCU). n pieces are provided in the buffer memory (BS), and the registered capacity of the second tag part is made larger than the registered capacity of the tag part of the buffer memory (BS), so that when the central processing unit (CPU) loads data to the buffer memory (BS), When the same address is registered in the second tag part, when all the ways in the second tag part are registered and the registered address and the registered address do not match, the second tag part is registered. The oldest address of the tag part of the above central processing unit (CPU) buffer memory (BS)
At the same time, the central processing unit (CPU) invalidates the address and at the same time registers the load address in the second tag section, thereby deleting the oldest address. By erasing, the second tag part is invalidated, and when the other processing device performs store access to the main storage unit (MSU), the main storage unit (MSU) and the buffer memory In order to match the contents of (BS), the other processing device performs a store access to the main storage unit (MSU), references the second tag part with the store address, and if a match is found, At the same time as sending data to the buffer memory and invalidating the buffer memory (BS),
Detection means for detecting that the store address valid (SAV) and the registered address valid (BFAV) of the central processing unit (CPU) for all addresses input to the second tag section are "off". 90 is the store address valid (SAV)
Only when it detects that both BFAV and registered address valid (BFAV) are off, it recognizes that there is no access to the second tag section, and stores the second tag section using the store address. When the store address is invalidated by referring to the second tag part and there is no match, the store address is not sent to the buffer memory BS, and the registered address of the second tag part is not sent to the buffer memory BS. A buffer memory coincidence control method is characterized in that control is performed so as not to stop memory access from other processing devices by not performing invalidation processing.