JPS6337601A - Chip resistor and manufacture of the same - Google Patents
Chip resistor and manufacture of the sameInfo
- Publication number
- JPS6337601A JPS6337601A JP61181759A JP18175986A JPS6337601A JP S6337601 A JPS6337601 A JP S6337601A JP 61181759 A JP61181759 A JP 61181759A JP 18175986 A JP18175986 A JP 18175986A JP S6337601 A JPS6337601 A JP S6337601A
- Authority
- JP
- Japan
- Prior art keywords
- resistor
- paste layer
- ceramic
- chip
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 13
- 239000000919 ceramic Substances 0.000 claims description 18
- 229910052573 porcelain Inorganic materials 0.000 claims description 11
- 238000000034 method Methods 0.000 claims description 4
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 4
- 238000005476 soldering Methods 0.000 description 3
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 238000004806 packaging method and process Methods 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 229910052718 tin Inorganic materials 0.000 description 2
- 239000004743 Polypropylene Substances 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 239000005388 borosilicate glass Substances 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 239000002003 electrode paste Substances 0.000 description 1
- 238000010304 firing Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- -1 polypropylene Polymers 0.000 description 1
- 229920001155 polypropylene Polymers 0.000 description 1
- 229910001925 ruthenium oxide Inorganic materials 0.000 description 1
- WOCIAKWEIIZHES-UHFFFAOYSA-N ruthenium(iv) oxide Chemical compound O=[Ru]=O WOCIAKWEIIZHES-UHFFFAOYSA-N 0.000 description 1
Landscapes
- Apparatuses And Processes For Manufacturing Resistors (AREA)
- Non-Adjustable Resistors (AREA)
- Details Of Resistors (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明は混成集積回路や複合部品の抵抗素子として、あ
るいは印刷配線基板に直接実装するチップ形抵抗器とそ
のｍ進方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a chip resistor that is mounted as a resistance element in a hybrid integrated circuit or a composite component, or directly mounted on a printed wiring board, and an m-adic method thereof.
（従来の技術）
従来のチップ形抵抗器はａ器性の基板の表面に抵抗膜が
形成されており、その基板の両端部において裏面と側面
に抵抗膜に接続される電極を形成したものである。(Prior art) A conventional chip resistor has a resistive film formed on the surface of an amorphous substrate, and electrodes connected to the resistive film are formed on the back and side surfaces of the substrate at both ends. be.
（発明が解決しようとする問題点）
従来のチップ形抵抗器では表と裏の区別があるため、実
装時にチップ形抵抗器を方向を定めてテープ詰めしたり
、マガジン詰めすることが必要となり、実装の工程が複
雑になる。(Problems to be Solved by the Invention) Conventional chip resistors have front and back sides, so it is necessary to set the direction of chip resistors and pack them with tape or magazines when mounting them. The implementation process becomes complicated.
また、生産ラインが連続でないので、製造コストが上昇
する問題もある。Furthermore, since the production line is not continuous, there is also the problem of increased manufacturing costs.
さらに、抵抗膜が表面に露出しているので、電極にメツ
キを施こすことができず、そのため電極の半田付は性を
向上させることが困難である。Furthermore, since the resistive film is exposed on the surface, the electrodes cannot be plated, and therefore it is difficult to improve the soldering properties of the electrodes.
本発明のチップ形抵抗器は、抵抗部を内在形にして表と
裏の区別のないチップ形抵抗器を作ることによって、実
装時にバルク化することができるようにするとともに、
−８極にメツキを施こして半口付は性を向上させること
ができるようにすることを目的とする。The chip resistor of the present invention can be made into a bulk at the time of mounting by making the resistor portion internal and making a chip resistor with no distinction between the front and back sides.
- The purpose of the 8-pole plate is to make it possible to improve the quality of the half-mouthed part.
また、本発明の製造方法では、生産ラインを連続化して
製造コストを低下させることを目的とする。Further, the manufacturing method of the present invention aims to reduce manufacturing costs by making the production line continuous.
（問題点を解決するための手段）
本発明のチップ形抵抗器では、その磁器体の内部に抵抗
を設け、磁器体内部の両端部には前記抵抗と接続される
内部電極を設け、磁器体外部の両端部には前記内部電極
に接続される外部電極を形成する。(Means for Solving the Problems) In the chip resistor of the present invention, a resistance is provided inside the ceramic body, and internal electrodes connected to the resistor are provided at both ends of the ceramic body. External electrodes connected to the internal electrodes are formed at both external ends.
また、本発明の製造方法では、キャリヤフィルム上に磁
器ペースト層を形成し、その磁器ペースト層上に内部電
極用の導電ペースト層を帯状に複数形成し、前記帯状導
電ペースト層に直交する方向に抵抗ペースト層を帯状に
複数形成し、その上に全面に磁器ペースト層を形成した
後、チップ状に切断して焼成し、チップの両端に外部電
極を形成する。Furthermore, in the manufacturing method of the present invention, a ceramic paste layer is formed on a carrier film, and a plurality of conductive paste layers for internal electrodes are formed in a strip shape on the ceramic paste layer, and a plurality of conductive paste layers for internal electrodes are formed in a direction perpendicular to the strip-shaped conductive paste layer. A plurality of resistor paste layers are formed in a band shape, a ceramic paste layer is formed on the entire surface thereof, and then cut into chips and fired to form external electrodes at both ends of the chips.
（実施例）
第１図及び第２図は本発明の一実施例を表わし、第１図
は第２図におけるＣ−Ｄ線位置での断面図であり、第２
図は第１図におけるＡ−Ｂ線位置での断面図である。(Embodiment) FIGS. 1 and 2 show an embodiment of the present invention, and FIG. 1 is a cross-sectional view taken along line C-D in FIG.
The figure is a sectional view taken along the line AB in FIG. 1.
２．４は磁器層であり、これらの磁器層２，４に挟まれ
て抵抗層６が形成されている。また、抵抗層６の両端部
には磁器層２，４に挟まれて抵抗層６に接続された内部
電極８．８が形成されている。抵抗ＩＩＪ６の両端と内
部電極８，８の端部は磁器層２，４の両端にまで延び、
磁器層２，４の両端の外部には内部電極８，８と接続さ
れている外部電極１２．１４が形成されている。2.4 is a ceramic layer, and a resistance layer 6 is formed between these ceramic layers 2 and 4. Furthermore, internal electrodes 8.8 are formed at both ends of the resistance layer 6, sandwiched between the ceramic layers 2 and 4 and connected to the resistance layer 6. Both ends of the resistor IIJ6 and the ends of the internal electrodes 8, 8 extend to both ends of the ceramic layers 2, 4,
External electrodes 12 and 14 are formed outside both ends of the ceramic layers 2 and 4 and are connected to the internal electrodes 8 and 8, respectively.
このチップ形抵抗器では、抵抗層６が磁器層２゜４に挟
まれて内在しているため、表と裏の区別がない、そのた
め外部電極１２．１４にメツキ、例えばニッケルと錫の
メツキ又は半田メツキを施こすことができる。In this chip resistor, since the resistance layer 6 is sandwiched between the ceramic layers 2.4, there is no distinction between the front and the back. Therefore, the external electrodes 12 and 14 are plated, for example, with nickel and tin plating or Solder plating can be applied.
次に、第３図により本発明の製造方法の一実施例を説明
する。Next, an embodiment of the manufacturing method of the present invention will be described with reference to FIG.
ポリプロピレンなどにてなるキャリヤフィルム２０上に
磁器ペースト層２を全面塗布し、乾燥させる。A porcelain paste layer 2 is applied over the entire surface of a carrier film 20 made of polypropylene or the like and dried.
その磁器ペースト層２上に内部電極となる導電ペースト
層８を印刷法により図で縦方向に帯状に塗布し、乾燥さ
せる。On the ceramic paste layer 2, a conductive paste layer 8, which will become an internal electrode, is applied in a strip shape in the vertical direction as shown in the figure by a printing method, and then dried.
次に抵抗ペースト層６を印刷法により導電ペースト層８
と直交する方向、すなわち図では横方向に帯状に塗布し
、乾燥させる。Next, the resistive paste layer 6 is printed onto the conductive paste layer 8.
It is applied in a band shape in the direction perpendicular to the direction, that is, in the horizontal direction in the figure, and allowed to dry.
次に抵抗ペースト層６及び導電ペースト層８を付与した
磁器ペースト層全面にさらに磁器ペースト層を塗布する
（図示略）。そして乾燥させる。Next, a ceramic paste layer is further applied to the entire surface of the ceramic paste layer to which the resistive paste layer 6 and the conductive paste layer 8 have been applied (not shown). And let it dry.
このようにしてキャリヤフィルム２ｏ上に磁器ペースト
層２、導電ペースト層８、抵抗ペースト層６及び磁器ペ
ースト層を積層したものを、記号２２で示されるように
、縦方向に関しては導電ペースト層８上を、横方向に関
しては抵抗ペースト層６の間の部分を切断し、チップ状
にする。そしてこのように切断されたチップを焼成する
。その後、必要により研磨バレルに入れて角を取る。な
お、キャリヤフィルム２０は積層体の切断前に剥離して
もよく、キャリヤフィルム２ｏをつけたまま焼成しても
よい、キャリヤフィルム２ｏは焼成中になくなる。In this way, the porcelain paste layer 2, the conductive paste layer 8, the resistive paste layer 6, and the porcelain paste layer are laminated on the carrier film 2o, as shown by symbol 22, on the conductive paste layer 8 in the vertical direction. In the lateral direction, the portion between the resistor paste layers 6 is cut to form a chip. The thus cut chips are then fired. Then, if necessary, put it in a polishing barrel to remove the corners. Note that the carrier film 20 may be peeled off before cutting the laminate, or the carrier film 2o may be fired with the carrier film 2o attached, and the carrier film 2o will disappear during firing.
その後、第１図及び第２図に示されるようにチップの両
端に外部電極のための電極ペーストを塗布して乾燥させ
、焼成して電極１２．１４とする。Thereafter, as shown in FIGS. 1 and 2, electrode paste for external electrodes is applied to both ends of the chip, dried, and fired to form electrodes 12 and 14.
外部電極１２．１４の半田付は性を向上させるために、
必要により電極１２．１４にメツキ、例えばニッケルと
錫のメツキ又は半田メツキを行なう。In order to improve the soldering properties of the external electrodes 12 and 14,
If necessary, the electrodes 12.14 are plated, for example with nickel and tin or solder.
磁器層２及び４としては通常使用されているアルミナ磁
器を使用することができる。抵抗６としては、例えば酸
化ルテニウムとホウ硅酸鉛ガラスを主体とした抵抗ペー
ストを使用することができる。内部電極８及び外部電極
１２．１４としては通常の電極材料であるＡｇ又はＡｇ
−Ｐｄを使用することができる。As the porcelain layers 2 and 4, commonly used alumina porcelain can be used. As the resistor 6, for example, a resistor paste mainly composed of ruthenium oxide and lead borosilicate glass can be used. The inner electrode 8 and the outer electrode 12.14 are made of Ag or Ag, which is a usual electrode material.
-Pd can be used.
磁器５２，４は厚みを大きくするために多層枯造にして
もよい。The porcelain 52, 4 may be multi-layered to increase the thickness.
（発明の効果）
本発明のチップ形抵抗器ではチップの表と裏の区別がな
くなるので、実装時にバルク化することができ、実装コ
ストが低下する。(Effects of the Invention) In the chip resistor of the present invention, there is no distinction between the front and back sides of the chip, so it can be made bulky during packaging, reducing packaging costs.
抵抗が内部に密閉されるので、湿度による抵抗の変化が
なくなる。Since the resistor is sealed inside, there is no change in resistance due to humidity.
抵抗が内部に密閉され露出しなくなるので、外部電極に
メツキを施こすことが可能となり、電極の半田付は性を
飛躇的に向上させることができる。Since the resistor is sealed inside and no longer exposed, it becomes possible to plate the external electrodes, and the soldering properties of the electrodes can be dramatically improved.
また、本発明の製造方法では、キャリヤフィルム上に磁
器層、電極、抵抗及び磁器層を積層して連続的に製造す
るので、生産ラインが連続化され、製造コストが低下す
る。Further, in the manufacturing method of the present invention, the ceramic layer, electrode, resistor, and ceramic layer are laminated on the carrier film and manufactured continuously, so the production line is made continuous and the manufacturing cost is reduced.
第１図及び第２図は本発明の一実施例を表わし、第１図
は第２図におけるＣ−Ｄ線位置での断面図であり、第２
図は第１図におけるＡ−Ｂ線位置での断面図、第３図は
本発明の製造方法を示す平面図である。
２．４・・・・・・磁器層、
６・・・・・抵抗、
８・・・・・・内部電極、
１２．１４・・・・・・外部電極。
２０・・・・・・キャリヤフィルム。1 and 2 show one embodiment of the present invention, and FIG. 1 is a sectional view taken along line C-D in FIG.
The figure is a sectional view taken along the line AB in FIG. 1, and FIG. 3 is a plan view showing the manufacturing method of the present invention. 2.4...Porcelain layer, 6...Resistor, 8...Internal electrode, 12.14...External electrode. 20...Carrier film.
Claims (2)
には前記抵抗と接続される内部電極を設け、磁器体外部
の両端部には前記内部電極に接続される外部電極を形成
したチップ形抵抗器。(1) A resistor is provided inside the porcelain body, internal electrodes connected to the resistor are provided at both ends inside the porcelain body, and external electrodes connected to the internal electrodes are provided at both ends outside the porcelain body. chip resistor.
その磁器ペースト層上に内部電極用の導電ペースト層を
帯状に複数形成し、前記帯状導電ペースト層に直交する
方向に抵抗ペースト層を帯状に複数形成し、その上に全
面に磁器ペースト層を形成した後、チップ状に切断して
焼成し、チップの両端に外部電極を形成するチップ形抵
抗器の製造方法。(2) forming a porcelain paste layer on the carrier film;
A plurality of conductive paste layers for internal electrodes are formed in a strip shape on the ceramic paste layer, a plurality of resistive paste layers are formed in a strip shape in a direction perpendicular to the strip conductive paste layer, and a ceramic paste layer is formed on the entire surface. A method for manufacturing a chip resistor in which the resistor is then cut into chips and fired to form external electrodes on both ends of the chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61181759A JPS6337601A (en) | 1986-07-31 | 1986-07-31 | Chip resistor and manufacture of the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61181759A JPS6337601A (en) | 1986-07-31 | 1986-07-31 | Chip resistor and manufacture of the same |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6337601A true JPS6337601A (en) | 1988-02-18 |
Family
ID=16106390
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61181759A Pending JPS6337601A (en) | 1986-07-31 | 1986-07-31 | Chip resistor and manufacture of the same |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6337601A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04130702A (en) * | 1990-09-21 | 1992-05-01 | Taiyo Yuden Co Ltd | Thermistor of chip type and manufacture thereof |
-
1986
- 1986-07-31 JP JP61181759A patent/JPS6337601A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04130702A (en) * | 1990-09-21 | 1992-05-01 | Taiyo Yuden Co Ltd | Thermistor of chip type and manufacture thereof |
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