JPS6337972B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a digital filter device in which coefficients of a transfer function are stored in advance and characteristics are made variable by switching the coefficients.

In recent years, digital filters consisting of multipliers, adders, delay circuits, etc. have been attracting attention instead of analog filters that can be realized using transistors, resistors, capacitors, coils, or operational amplifiers. A major feature of this digital filter is that filters with many characteristics can be easily constructed using the same circuit.

In Figure 1, the transfer function is H(Z)=K・1+a ₁ Z ^-1 +a ₂ Z ^-2 /1+b ₁ Z ^-1 +b ₂ Z ^-2
...A low-pass filter (or high-pass filter) with variable cutoff frequency is shown as an IIR (infinite response) digital filter expressed by equation (1).
In FIG. 1, numeral 1 is an adder to which an input signal is supplied, and the output of this adder 1 is supplied to an adder 2 and also to a delay circuit 3 which delays by a unit time. The output of this delay circuit 3 is then supplied to multipliers 4 and 5. This multiplier 4 has ROM
(Read-only memory) 6 further supplies data b ₁ addressed and selectively outputted by cut-off frequency data c, and the input signal is multiplied by b ₁ and applied to adder 1 . Note that this input signal instructs the adder 1 to perform subtraction. Further, the multiplier 5 is further supplied with data _a1 selectively output from the ROM 6, and the input signal is
a is multiplied by ₁ and given to adder 2. Then, the output of the delay circuit 3 is applied to multipliers 8 and 9 via a delay circuit 7 which further delays the signal by a unit time. The multipliers 8 and 9 are further supplied with data b ₂ and a ₂ supplied from the ROM 6, respectively, and the input signal is b ₂
A is multiplied _{by 2} and given to adders 1 and 2. Note that the signal given to the adder 1 is designed to instruct subtraction. And the output of the adder 1,
The output of the adder 2 which is supplied with the outputs of the multipliers 5 and 9 and adds them together is given to the multiplier 10 which is supplied with the output K of the ROM 6 selected by the cut-off frequency c, and is multiplied by K. This becomes the output signal.

However, when changing the cut-off frequency c from a filter with characteristics "A" to a filter with characteristics "B", if each coefficient changes significantly, the output change will be large and undesirable. Particularly when such a digital filter device is applied to an electronic musical instrument or various types of audio equipment, there are drawbacks such as an audible sense of unnaturalness.

This invention was made in view of the above points,
A digital filter device in which coefficients of a transfer function are stored in advance and characteristics are varied by switching the coefficients, and the timing of switching the coefficients is determined based on an input signal to the digital filter device. The purpose is to provide

Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 2 shows the circuit configuration of this embodiment, but for the purpose of simplifying the explanation, the same parts as in FIG. 1 are given the same reference numerals and the explanation thereof will be omitted. That is, 11 in FIG. 2 is a coincidence detection circuit as shown in FIG. 3. This coincidence detection circuit 11 receives the top 6 of the input signals supplied to this digital filter device.
Bits are given. The input signal applied to the digital filter device is controlled so that its absolute value does not exceed 1, as shown in FIG.
The most significant bit is the sign bit, and the following 7 bits are weighted from 2 ^-1 to 2 ^-7 , making up a total of 8 bits of data. Further, this digital filter device performs calculations using two's complement representation.

Therefore, the coincidence detection circuit 11 operates as an AND circuit 12 that detects that all 6-bit inputs are "1".
, inverters 13 ₁ to 13 ₆ that invert each of these 6-bit inputs, and inverters 13 ₁ to 13 ₆
It has an AND circuit 14 for detecting that all bit outputs are "1", and an OR circuit 15 to which the outputs of the AND circuits 12 and 14 are supplied.

The output of this OR circuit 15 is applied to the latch 16 as a read control signal R. For example, this latch 16 performs a read operation at the timing of the rise of the read control signal R. The latch 16 is supplied with the at-off frequency data c (consisting of a plurality of bits), read by the read control signal R, and the output, that is, the data c', specifies an address for the ROM 6.

Therefore, the ROM 6 is addressed by the data c' supplied from the latch 16 and has the coefficients a ₁ ,
a ₂ , b ₁ , b ₂ , and K are selectively output.

Next, the operation of this embodiment will be explained. That is,
Now, if a digital filter with characteristic "A" is constructed by selecting each coefficient of the transfer function expressed by equation (1) to a predetermined value, the transfer function will be written as the following equation (2) for convenience of explanation. .

H _A (Z)=K _A・1+a _1A Z ^-1 +a _2A Z ^-2 /1+b _1A Z ^-1 +b _2A Z
^-2 ...Equation (2) That is, each coefficient a ₁ , a ₂ , b ₁ , b ₂ , K is _{a 1A} , a _2A , b _1A ,
The values of b _2A and K _A will be read from the ROM6.

And these coefficients a _1A , a _2A , b _1A , b _2A , K _A are
Assume that the signals are supplied to multipliers 5, 9, 4, 8, and 10, respectively. From this state, the cutoff frequency is c _B
When configuring a digital filter with characteristic “B” by changing the transfer function as shown in equation (3) below, H _B (Z)=K _B・1+a _1B Z ^-1 +a _2B Z ^{- 2} /1+b _1B Z ^-1 +b _2B Z
^-2 ...Formula (3) Input data c _B is supplied to the latch 16, and its output data is data c _A ′ (≠c _B ).

In that case, when the input signals to this digital filter device have the same content in their upper 6 bits, in other words, the input data falls within the range of "0.0234375 to -0.0546875" as shown in FIG. At the same timing, the read control signal R is output from the coincidence detection circuit 11, and at the rising timing of the read control signal R, the latch 16 is commanded to perform a read operation.

As a result, the cutoff frequency data c _B will be stored in the latch 16, and the coefficients a _1B , a _2B , b _1B , b _2B , and K _B will be output from the ROM 6, and therefore, The digital filter device operates as a digital filter with a transfer function expressed by the above equation (3).

As described above, in the case of this embodiment, the input signal to the ROM 6 is changed only when the input signal to the digital filter device changes to the range of "0.023437 to -0.0546875" including "0", that is, when the input signal level is low. By making address designation changeable, it is possible to minimize the transient effects when changing the characteristics of the digital filter device.

In the above embodiment, the timing of changing the characteristics of the digital filter device is determined based on the upper 6-bit data of the input signal to the digital filter device, but the number of bits of the data to be compared is not limited to this. .

Further, in the above embodiment, the timing of changing the characteristics was determined when the input signal of the digital filter device changed to within a predetermined level including the numerical value "0"; If you operate it at the timing of descent,
The characteristics are changed at the timing when the above-mentioned predetermined level is passed.

Furthermore, although the above embodiments have been explained with reference to a second-order/second-order R digital filter device, the present invention can also be applied to a higher-order digital filter device, and the present invention can also be applied to digital filter devices having various other characteristics. It is possible to apply the present invention.

It goes without saying that various other modifications and applications can be made without departing from the gist of the present invention.

As described in detail above, in a digital filter device in which coefficients of a transfer function are stored in advance and characteristics are varied by switching the coefficients, the timing of switching the coefficients is determined by inputting an input signal to the digital filter device. By detecting that the waveform data of has become "0" or a value close to it, there is an advantage that transient effects at the time of coefficient switching are suppressed. In addition, when this digital filter device is applied to electronic musical instruments or various audio equipment, the output sound will change audibly smoothly even when changing characteristics, eliminating unnaturalness when switching, etc. Very effective.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the circuit configuration of a conventional digital filter device, FIG. 2 is a circuit diagram of a digital filter device showing an embodiment of the present invention, and FIG. 3 is a diagram showing the main part configuration of FIG. FIG. 4 is a diagram for explaining input data of this embodiment. 1, 2... Adder, 3, 7... Delay circuit, 4,
5, 8, 9, 10... Multiplier, 6... ROM, 1
1... Match detection circuit, 16... Latch.

Claims (1)

[Claims] 1. In a digital filter device that filters an input signal consisting of waveform data having positive and negative values with the numerical value "0" as a reference level according to a predetermined transfer function, according to the characteristics: a switching means for switching coefficients of the transfer function; and a switching device that determines predetermined bit data of the waveform data of the input signal to the digital filter device, so that the waveform data corresponds to the numerical value "0" or its vicinity. A digital filter device comprising: a detection means for detecting that the coefficient has reached a value of 0.1, and a switching timing control means for controlling the timing of coefficient switching of the switching means in accordance with the detection result of the detection means.