JPS6339941U - - Google Patents
Info
- Publication number
- JPS6339941U JPS6339941U JP13407286U JP13407286U JPS6339941U JP S6339941 U JPS6339941 U JP S6339941U JP 13407286 U JP13407286 U JP 13407286U JP 13407286 U JP13407286 U JP 13407286U JP S6339941 U JPS6339941 U JP S6339941U
- Authority
- JP
- Japan
- Prior art keywords
- electronic component
- circuit wiring
- mounting structure
- base
- wiring formed
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
- H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
- H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink
Landscapes
- Wire Bonding (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13407286U JPS6339941U (mo) | 1986-09-01 | 1986-09-01 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13407286U JPS6339941U (mo) | 1986-09-01 | 1986-09-01 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6339941U true JPS6339941U (mo) | 1988-03-15 |
Family
ID=31034971
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13407286U Pending JPS6339941U (mo) | 1986-09-01 | 1986-09-01 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6339941U (mo) |
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1986
- 1986-09-01 JP JP13407286U patent/JPS6339941U/ja active Pending