JPS6340363A - random access memory - Google Patents

Abstract

(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a random access memory, and more particularly to an M03 random access memory including a pair of complementary first and second bit lines forming a folded bit line. Regarding.

[Prior art] Figure 4 shows a dynamic MO with a conventional folded bit line configuration.
FIG. 8 is a plan view of a memory cell section in 8-RAM.

In FIG. 4, a plurality of bits tfA1 are formed of a first aluminum wiring layer and are provided in parallel. These pits 11
A word line 3 made of a second polysilicon layer is formed so as to intersect with the second polysilicon layer.

A cell plate 2 constituting a memory capacitor made of a first polysilicon layer is formed near the intersection of the bit line 1 and the word line 3. A region 4 covered with a field oxide film is formed.

Note that region 4 is connected to bit line 1 through contact 5.

Conventional dynamic MO8-R configured as described above
In AM, when accessed via word $113,
Information in the memory cell is read onto bit line 1.

[Problems to be solved by the invention] By the way, the dynamic MO8- shown in FIG.
In the RAM, if the capacitance of the bit line 1 is Ca and the capacitance of the memory cell is C5, the potential difference read on the bit l111 of the RAM is C=/CB, which is a very small value. For this reason, it was necessary to use a highly sensitive sense amplifier to detect successive charges. However, as higher integration progresses, the distance between the capacitance of bit 11 and the adjacent bit lines becomes increasingly large, and the capacitance between adjacent bit lines increases, resulting in an increase in the total bit line capacity. death,
There was a problem that the successive potential difference decreased.

Therefore, the main object of the present invention is to provide a random access memory in which bit lines are configured so that the line-to-line capacity of adjacent bits does not increase even as the degree of integration increases.

Means for Solving Problems Between 1 and 9] 'The present invention is a random access memory including complementary first and second pairs of pit lines constituting folded bit lines, wherein the complementary pit line pair Each layer is formed from different first and second conductive layers in a plane perpendicular to the line drawing direction, and the same layers are not adjacent to each other.

[Function] In the random access memory according to the present invention, since the first and second pit line pairs are each composed of different first and second conductive layers, the bit S! Even if the spacing is narrow, the line-to-line capacitance of the bit lines can be reduced.

[Embodiment J of the invention FIG. 1 is a diagram showing the configuration of an embodiment of the present invention, FIG. 2 is a plan view of the shaded area X in FIG. 1, and FIG. It is a sectional view along ■-■.

First, referring to FIG. 1, in one embodiment of the present invention, a first bit line 11 has a portion 1 formed from a third polysilicon layer and a portion 8 formed from a fourth polysilicon layer. It is composed of Also, the first bit 4'j111
The second bit line 12 paired with the second bit line 12 is constituted by a portion 6 formed from the fourth polysilicon layer and a portion 9 formed from the third polysilicon layer. That is, the first
Portion 1 and second bit J61 constituting bit line 11 of
As shown in FIG. 3, the third polysilicon layer and the fourth polysilicon layer in which the portion 6 constituting the bit line 2 is formed are different in the plane perpendicular to the extending direction of the bit line. .

Similarly, the portion 8 constituting the first bit line 11 and the portion 9 constituting the second bit line 12 have different layers in the plane perpendicular to the bit line extending direction. Therefore, the portion 1 of the first bit line 11 and the portion 6.15 of the second bit line 12, the portion 8 of the first bit line 11, and the portion 9 of the second bit line 72 are the interlayer film of the layer. Since the distance between adjacent bits can be increased by the amount of , the capacity between bits m in each can be reduced. Also, the first and second
The bits 1111 and 12 have the same parasitic capacitance because they are both formed by the third polysilicon layer and the fourth polysilicon layer having the same length.

Note that the first bit line 11 and the second bit line 1i11
2 are each connected to a sense amplifier 10, and a first bit line 11 and a word line 3 crossing it are connected to a memory cell. In this way, by increasing the distance between the first and second bit lines 11 and 12 and making them the same length, malfunction of the sense amplifier 1o and the amount of read signal on each bit line 11 and 12 can be prevented. No change will occur.

Note that in the above description, the first and second bit lines 11
and 12 to the third polysilicon and fourth polysilicon, respectively.
Although it is made of polysilicon, it is not limited to this, and may be formed of polycide, a silicide layer, or aluminum wiring.

[Effects of the Invention] As described above, according to the present invention, adjacent bit lines are formed in different wiring layers and complementary bit lines are configured to have the same capacitance. A large amount of random access memory can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the configuration of an embodiment of the present invention. FIG. 2 is also a plan view. Figure 3 is the line ■-■ of Figure 2.
FIG. FIG. 4 is a plan view of a conventional random access memory. In the figure, 1.8 is a portion constituting the first bit line;
3 is a word line, 6.9 is a portion constituting a second bit line, 1o is a sense amplifier, 11 is a first bit line, and 12 is a second bit line.

Claims (3)

[Claims] (1) Complementary first and second lines forming a folded bit line
In the random access memory, the first and second bit line pairs are formed in different first and second conductive layers in a plane perpendicular to the bit line extending direction, and A random access memory characterized in that it is provided so as not to be adjacent to each other in the same conductive layer. (2) The random bit line pair according to claim 1, wherein the lengths of regions formed in the first and second conductive layers are equal to each other. access memory. (3) The first bit line consists of a third and fourth bit line, the third and fourth bit lines are formed in different layers, and the second bit line consists of a fifth and a fourth bit line. a sixth bit line, the fifth bit line is formed in a different layer from the third bit line, and the sixth bit line is formed in the fourth and fifth bit lines.
3. The random access memory according to claim 1, wherein the random access memory is formed in a layer different from that of the bit lines.