JPS6340897U - - Google Patents
Info
- Publication number
- JPS6340897U JPS6340897U JP13508786U JP13508786U JPS6340897U JP S6340897 U JPS6340897 U JP S6340897U JP 13508786 U JP13508786 U JP 13508786U JP 13508786 U JP13508786 U JP 13508786U JP S6340897 U JPS6340897 U JP S6340897U
- Authority
- JP
- Japan
- Prior art keywords
- mos transistors
- gates
- transistor
- stage mos
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000003990 capacitor Substances 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 4
- 230000003071 parasitic effect Effects 0.000 description 1
Description
第１図はこの考案の一実施例による昇圧回路を
示す図、第２図は従来の昇圧回路を示す図、第３
図は該回路の動作時の各接続点の電位の変化を示
す波形図である。
図において、１はＮＭＯＳトランジスタ、２は
キヤパシタ、３は寄生容量、４，５はパルス入力
端子、６は出力端子、１１は前段のＮＭＯＳトラ
ンジスタ、１２はインバータ、２１は後段のＮＭ
ＯＳトランジスタ、３０は端子である。なお図中
同一符号は同一又は相当部分を示す。
FIG. 1 is a diagram showing a booster circuit according to an embodiment of this invention, FIG. 2 is a diagram showing a conventional booster circuit, and FIG. 3 is a diagram showing a conventional booster circuit.
The figure is a waveform diagram showing changes in potential at each connection point during operation of the circuit. In the figure, 1 is an NMOS transistor, 2 is a capacitor, 3 is a parasitic capacitance, 4 and 5 are pulse input terminals, 6 is an output terminal, 11 is a front-stage NMOS transistor, 12 is an inverter, and 21 is a rear-stage NM
The OS transistor 30 is a terminal. Note that the same reference numerals in the figures indicate the same or equivalent parts.
Claims (1)
トランジスタと、該トランジスタのソースと回路
の出力端子との間に直列に接続されたダイオード
接続の第１〜第ｎ段のＭＯＳトランジスタと、上
記出力端子と接地間に挿入された後段のＭＯＳト
ランジスタと、上記第１〜第ｎ段のＭＯＳトラン
ジスタのゲートに接続されクロツク信号を受ける
キヤパシタとを備えた昇圧回路において、 上記前段のＭＯＳトランジスタのゲートに電圧
を印加するための端子と、 該端子と上記後段のＭＯＳトランジスタのゲー
ト間に接続されたインバータとを備えたことを特
徴とする昇圧回路。[Scope of claim for utility model registration] Front-stage MOS whose drain is connected to the power supply
a transistor, diode-connected first to nth stage MOS transistors connected in series between the source of the transistor and the output terminal of the circuit, and a subsequent stage MOS transistor inserted between the output terminal and ground; , and a capacitor connected to the gates of the first to nth stage MOS transistors and receiving a clock signal, the step-up circuit comprising: a terminal for applying a voltage to the gates of the preceding stage MOS transistors; 1. A booster circuit comprising: an inverter connected between gates of MOS transistors in a subsequent stage.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13508786U JPS6340897U (en) | 1986-09-03 | 1986-09-03 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13508786U JPS6340897U (en) | 1986-09-03 | 1986-09-03 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6340897U true JPS6340897U (en) | 1988-03-17 |
Family
ID=31036941
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13508786U Pending JPS6340897U (en) | 1986-09-03 | 1986-09-03 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6340897U (en) |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57203287A (en) * | 1981-06-10 | 1982-12-13 | Nec Corp | Ratio type gate circuit with power down function |
| JPS58177599A (en) * | 1982-04-12 | 1983-10-18 | Toshiba Corp | Semiconductor integrated circuit device |
| JPS59186200A (en) * | 1983-04-04 | 1984-10-22 | インタ−ナショナル ビジネス マシ−ンズ コ−ポレ−ション | On-chip high voltage power feeder |
| JPS6050697A (en) * | 1983-08-30 | 1985-03-20 | Toshiba Corp | semiconductor integrated circuit |
| JPS6069897A (en) * | 1983-09-08 | 1985-04-20 | Toshiba Corp | Non-volatile semiconductor memory device |
| JPS60223096A (en) * | 1984-04-18 | 1985-11-07 | Toshiba Corp | Semiconductor integrated circuit |
-
1986
- 1986-09-03 JP JP13508786U patent/JPS6340897U/ja active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57203287A (en) * | 1981-06-10 | 1982-12-13 | Nec Corp | Ratio type gate circuit with power down function |
| JPS58177599A (en) * | 1982-04-12 | 1983-10-18 | Toshiba Corp | Semiconductor integrated circuit device |
| JPS59186200A (en) * | 1983-04-04 | 1984-10-22 | インタ−ナショナル ビジネス マシ−ンズ コ−ポレ−ション | On-chip high voltage power feeder |
| JPS6050697A (en) * | 1983-08-30 | 1985-03-20 | Toshiba Corp | semiconductor integrated circuit |
| JPS6069897A (en) * | 1983-09-08 | 1985-04-20 | Toshiba Corp | Non-volatile semiconductor memory device |
| JPS60223096A (en) * | 1984-04-18 | 1985-11-07 | Toshiba Corp | Semiconductor integrated circuit |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP2531267B2 (en) | Charge pump | |
| JPH0324092B2 (en) | ||
| JPS6340897U (en) | ||
| JPH082016B2 (en) | Boost circuit | |
| JPS59169B2 (en) | flip flop circuit | |
| JPH021924U (en) | ||
| JPS61104783U (en) | ||
| JPS62103361U (en) | ||
| JPS6170431U (en) | ||
| JPH0476736U (en) | ||
| JPS621466U (en) | ||
| JPS61202973U (en) | ||
| JPH0330000Y2 (en) | ||
| JPS63160087U (en) | ||
| JPS6383834U (en) | ||
| JPS62151223U (en) | ||
| JPS63146487U (en) | ||
| JPH038125B2 (en) | ||
| JPH0157822U (en) | ||
| JPS63227211A (en) | boost circuit | |
| JPS62167427U (en) | ||
| JPS5973846U (en) | semiconductor circuit | |
| JPS6157631U (en) | ||
| JPS61195786U (en) | ||
| JPS62203529U (en) |