JPS6343773B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to an arithmetic control device that can access memory according to the data length of data. Generally, in a microprogram-controlled electronic computer, data stored in a memory is read or written by specifying the type of memory access by the microprogram. That is, memory access includes reading and writing, and data is stored in the memory in units of whole words, half words, and bytes. Therefore, the types of memory access are full-word writing, half-word reading, and
Like byte writing, it is specified by the microprogram. However, for example, decimal values can have any data length in bytes. Therefore, when writing data with such a configuration, the type of memory access must be determined based on the data length and the location of the stored data. Furthermore, in the case of reading, reading is possible if all words are read. However, the response speed of the memory may differ depending on whether the data is stored at a full-word boundary. In this case, in order to perform special processing using firmware, the type of memory access must be changed in consideration of response speed. Conventionally, processes shown in the flowcharts of FIGS. 1, 2, and 3 have been considered as a process for eliminating the above-mentioned defects. That is, FIG. 1 shows that byte writing is performed. This consists of a step in which the memory address is set, a step in which a byte is written, a step in which 1 is added to the memory address to write the next byte, and a step in which the data length is specified to specify which boundary to write to. It consisted of a step of subtracting 1 and a step of determining whether the data length has become 0. Since this method can only process one byte at a time, it takes a lot of time. Another possible method is to change the type of writing based on the data length and the location of the data in the memory, as shown in FIG. That is, in this case, write processing is performed separately into an area for full-word writing, an area for half-word writing, and an area for byte writing. However, this method requires several steps for determination, and also requires controlling the data register for writing data into memory in accordance with the data length. Furthermore, in the case of reading data, it is possible to read all data by reading all words. However, if the location where the data is stored is not on a full-word boundary, it takes a long time to read the data. Furthermore, if the data is processed in consideration of the data length, the method shown in FIG. 3 will be obtained. In other words, the lowest two bits of the data memory address are (1, 1), (1, 0), (40, 1), and (0, 0) for determining the type of memory access. The number of steps is large and it takes time. Furthermore, regardless of whether the above-mentioned writing or reading is performed, control is required to check each time whether processing for the required data length has been completed. Therefore, no matter which method is used,
This was time consuming and complicated to control. The present invention was made in view of the above drawbacks.
Processes arbitrary data in bytes, such as decimal values, at high speed, and checks whether processing for the required data length has been completed using hardware by installing a circuit. An object of the present invention is to provide an arithmetic control device that can shorten the time required for processing. Next, the present invention will be explained in detail using the drawings.
FIG. 4 is a block diagram showing one embodiment of the present invention. Reference numeral 1 is a control bus. This control bus 1 is a path for transferring control signals such as microinstructions. 2, 3, and 4 are data buses. The data bus 2 is a path for transferring data of calculation results, and the data buses 3 and 4 are paths for transferring data used in calculations. 5 is the main memory. 6 is a memory control section. Memory control unit 6
has the function of controlling memory access timing and has registers that hold addresses and data for memory access. Reference numeral 7 denotes a control storage section in which a macro program is stored. A gate 8 prevents the output signal from the control storage section 7 from being output to the control bus 1 when an inhibit signal is input from the terminal INHIB. 9 and 10 are registers. register 9
stores the data length, and the register 10 stores the two least significant bits of the data address in the main memory 5. 11 is a first memory. This first memory 10 is a ROM,
It has a function of determining the type of memory access from the lowest two bits of the address of the data in the main memory stored in the register 10 and the data length stored in the register 9. 12 is a second memory. The second memory 12 is a ROM and has a function of determining numerical data for updating the address for reading the next data from the main memory 5 in response to a certain type of memory access. . Reference numeral 13 denotes a gate, which has a function of inhibiting the output of the first memory during a certain operation, that is, an operation in which the type of memory access is specified by a microprogram. 14 and 15 are registers. Register 14 is first memory 1
It holds the signal output from 1 that specifies the type of memory access. The register 15 holds the signal output from the second memory. 16 and 17 are adders and subtracters. Adder/subtractor 16
is used to add or subtract the data length stored in register 9 and the numerical data stored in register 15. The adder/subtracter 17 performs addition/subtraction between the lowest two bits of the address of the data in the main memory 5 stored in the register 10 and the numerical data stored in the register 15. 18, 19, and 20 are data selectors. The data selector 18 selects whether to input an initial value to the register 9 or input the result calculated by the adder/subtractor 16. The data selector 19 inputs an initial value to the register 10 or inputs the initial value to the adder/subtractor 1.
7 is for selecting whether to input the calculated result. The data selector 20 selects whether to output the numerical data stored in the register 15 to the data bus 3 or to output the calculation result of the adder/subtractor 16 to the data bus 3. A gate 21 has a function of outputting the data output from the data selector 20 to the data bus. 22 is a calculation section. This calculation unit 22 calculates data on the data bus 3 and data bus 4 and sends the data to the data bus 2. Next, the operation of this embodiment will be explained using decimal addition as an example. The flow of the microprogram for decimal addition is shown in FIGS. 5 and 6. Further, the type of memory access output from the first memory and the numerical data for updating the address output from the second memory are as shown in Tables 1 and 2 below.

【table】

【table】

[Table] As is clear from the figure, the microprogram is (A)
Second operand fetch that reads the second operand from memory and stores it in the specified register, (B)
It consists of a part that reads the first operand from memory, performs an operation on the second operand that was previously read, and (C) writes the result of the operation to memory. This 3
I will explain it in two parts. (A) Second operand fetch In the initial setting, the data length is data selector 18.
is stored in register 9 via . In the memory address set, the lowest two bits of the data address in the main memory 5 are stored in the register 10 via the data selector 19. When memory read is specified, register 9
The data length stored in the register 10 and the lowest two bits of the address stored in the register 10 are input to the first memory 11. In the first memory 11, the type of memory access is determined based on this. The type of memory access is primarily held in the register 14 and sent to the control bus 1 via the gate 13. At this time, an inhibit signal is input to the gate 8, and no microprogram is sent out from the control storage section 7. In memory address update, the data length stored in register 9 and the lowest two addresses stored in register 10 are
one bit is input to the second memory 12.
Numerical data to be added to the previously read address is sent from the second memory 12 in order to read the next data. This numerical data is
It is temporarily held in the register 15 and sent to the data bus 3 via the data selector 20 and gate 21. The address used for the previous memory access is transferred from the memory control unit 6 to the data bus 4.
is being sent to. This address and the numerical data on the data bus 3 are added by the arithmetic unit 20 and stored in the memory control unit 6 via the data bus 2. At this time, the adder/subtractor 16 calculates the remaining data length from the data length and the numerical data required for the memory address. This data length is stored in the register 9 via the data selector 18. The adder/subtracter 17 calculates the two least significant bits of the new address from the two least significant bits of the previous address and the numerical data required for the memory address. These two bits are stored in register 10 via data selector 19. Thereafter, memory access is repeated in the same manner, and necessary data is read out. At this time, a signal instructing a return operation is sent from the first memory to the control bus 1 via the register 14 and gate 13. This returns the microprogram to the main routine. (B) Decimal addition In this routine as well, the data length is set in register 9 in the initial setting, and the two lowest bits of the address are set in register 10 in memory address setting. Below, the same operation as described in (A) is performed, and the second operand and the first operand are added. When the calculation of the required data length is completed, a signal instructing a return operation is output from the first memory 11. In this way, the microprogram returns to the main routine. (C) Result writing In this case as well, as in the cases (A) and (B) described above, the cut-off period setting, memory address set, memory write, and memory address update are repeated. When the write operation is completed in this way, a return signal is output and the microprogram returns to the main routine. As explained above, according to the present invention, when processing data of an arbitrary data length in bytes, such as decimal values, the data length and the data stored in main memory are Since this is performed by a circuit (first memory) that determines the type of memory access based on the two least significant bits of the data address, optimal control is performed and speed is increased.
Furthermore, since the above circuit checks whether the subroutine has ended and issues a return signal, it also serves as a check every time, making it highly efficient. In addition, when the data is not arbitrary in bytes,
Control is performed by a microprogram sent from the control storage section 7.

[Brief explanation of the drawing]

Figures 1, 2, and 3 are flowcharts for conventional data processing, Figure 4 is a block diagram of an embodiment of the present invention, and Figures 5 and 6 are for data processing of the present invention. This is a flowchart. 5... Main memory, 11... First memory, 12... Second memory, 13... Gate.

Claims (1)

[Scope of Claims] 1. In a microprogram-controlled electronic computer, a main memory in which data is stored in whole words, half words, and bytes, and from the access start position of data to be accessed to the end position of this data. The data length and the lowest two bits of the address of the access start position in the main memory are input, and this data is accessed from the access start position in whole word units or in half word units. inputting a first memory that determines whether to access the memory, access the memory in units of bytes, or return to the main routine, the data length and the two bits;
In response to a predetermined memory access determined by said first memory. a second memory for determining numerical data for determining the address of the next access start position in the main memory; inputting the data length and the numerical data;
An arithmetic control device comprising: calculation means for calculating a data length from the next access start position to the end position.