JPS6345126B2 - - Google Patents
Info
- Publication number
- JPS6345126B2 JPS6345126B2 JP56201893A JP20189381A JPS6345126B2 JP S6345126 B2 JPS6345126 B2 JP S6345126B2 JP 56201893 A JP56201893 A JP 56201893A JP 20189381 A JP20189381 A JP 20189381A JP S6345126 B2 JPS6345126 B2 JP S6345126B2
- Authority
- JP
- Japan
- Prior art keywords
- signal
- maximum
- period
- initial value
- sequence
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/84—Generating pulses having a predetermined statistical distribution of a parameter, e.g. random pulse generators
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56201893A JPS58101515A (ja) | 1981-12-14 | 1981-12-14 | 最大周期列信号の初期値設定回路 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56201893A JPS58101515A (ja) | 1981-12-14 | 1981-12-14 | 最大周期列信号の初期値設定回路 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS58101515A JPS58101515A (ja) | 1983-06-16 |
| JPS6345126B2 true JPS6345126B2 (de) | 1988-09-08 |
Family
ID=16448568
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56201893A Granted JPS58101515A (ja) | 1981-12-14 | 1981-12-14 | 最大周期列信号の初期値設定回路 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58101515A (de) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1989009471A2 (en) * | 1988-04-01 | 1989-10-05 | Digital Equipment Corporation | Memory selftest method and apparatus |
| CN107145332B (zh) * | 2017-04-28 | 2021-06-29 | 郑州云海信息技术有限公司 | 一种OpenCL内核程序中随机数产生方法及装置 |
-
1981
- 1981-12-14 JP JP56201893A patent/JPS58101515A/ja active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS58101515A (ja) | 1983-06-16 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR910005064A (ko) | 제어신호 발생 방법 및 장치 | |
| JPWO1999040450A1 (ja) | 半導体デバイス試験装置 | |
| GB2080551A (en) | Device for testing a circuit comprising sequential and combinatorial parts | |
| US3482027A (en) | Automatic rhythm instrument | |
| EP0113181A1 (de) | Digitale Zufallsfehlergenerator-Anordnung | |
| US5966313A (en) | Apparatus and method for generating random numbers | |
| KR970031301A (ko) | 펄스폭변조신호 출력회로 | |
| JPH0651028A (ja) | テスト・パターン発生装置 | |
| AU3448093A (en) | Testing of a data-transmission line using dual cross-correlation to assess the number of defective bits | |
| JPS6345126B2 (de) | ||
| US4173000A (en) | Simulated VLF/LF noise generator | |
| CA2045619A1 (en) | Method and apparatus for preventing external detection of signal information | |
| JPH10197610A (ja) | ノイズ発生装置およびそれを用いた波形生成装置 | |
| JP3039316B2 (ja) | 信号発生装置 | |
| EP0903650B1 (de) | Zeitintervallgeber mit Zeitzähler, Register und Koinzidenzdetektorschaltung sowie Verfahren zur Steuerung eines Schaltungsausgangs unter Einsatz eines derartigen Zeitintervallgebers | |
| US4179970A (en) | Automatic arpeggio for multiplexed keyboard | |
| SU1691839A2 (ru) | Генератор псевдослучайных чисел | |
| US5224104A (en) | Real-time address switching circuit | |
| US5521952A (en) | Pulse counter circuit and pulse signal changeover circuit therefor | |
| JPH06209355A (ja) | 伝送検査用信号発生回路 | |
| JPH07154258A (ja) | A/dコンバータをテストする方法と装置 | |
| KR102077401B1 (ko) | 인버터 셀의 강도를 이용한 실난수 발생기 | |
| SU1210209A2 (ru) | Генератор псевдослучайных последовательностей импульсов | |
| JP2846356B2 (ja) | Ic試験装置 | |
| JP2762525B2 (ja) | 擬似信号発生装置 |