JPS6346582B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to semiconductor devices, and particularly to bipolar transistors for ultra-high-speed logic LSIs.

Traditionally, transistors with an oxide film isolation structure have been widely used as bipolar transistors for ultra-high-speed logic LSIs, such as the one from Bell Laboratories.
OXIM (Oxide Isolated Monolith) structure, Fair-Child Semiconductor's isoplanar structure, Siemens' OXIS (Oxide
These structures reduce the element area to about 60% and the collector-base junction area to about 40% compared to the conventionally widely used TTL transistor. Ultra high speed logic LSI
It has become possible to construct circuits with extremely low integration, delay time, and power product.

Below, this type of fully implanted self-aligned contact (Fully Implanted Self-Aligned Contact)
This will be explained using a transistor with ISAC-) structure as an example. FIG. 1 is a longitudinal sectional view of the main parts of a conventional ISAC-structure transistor. In Figure 1, 1 is a relatively low impurity concentration (10 ¹⁴ cm ^-3 )
A semiconductor substrate 2 made of P-type silicon is formed by ion implantation and annealing of antimony or arsenic into a predetermined portion of the upper surface of the semiconductor substrate 1, and a portion of the semiconductor substrate 2 floats onto the N-type epitaxially grown semiconductor layer described below. 3 is an epitaxially ^grown semiconductor layer (hereinafter abbreviated as "epitaxial layer") formed on the semiconductor substrate 1 including the buried collector region 2 and made of N type silicon; 5 is a P-type channel cut region formed in a portion of the upper surface of the semiconductor substrate 1 where the buried collector region 2 is not formed, and 5 is a P-type channel cut region formed in a portion of the upper surface of the semiconductor substrate 1 where the buried collector region 2 is not formed. Alternatively, the insulating isolation film 6 is formed by removing the silicon in that part and filling it with glass.Boron ion implantation and annealing are performed on the collector region side of the part that should become the base region of the epitaxial layer 3, which will be described later. The formed P ⁺ type active base region 7 is formed by ion implantation and annealing of boron at a higher concentration than the active base region 6 on the side opposite to the later-described collector region of the portion that should become the base region of the epitaxial layer 3. The inactive base region 8 of the P ⁺ type formed on the epitaxial layer 3 surrounded by the insulating isolation film 5 is subjected to annealing of the active base region 6 and the inactive base region 7.
An insulating film such as a silicon oxide film formed by a CVD method or the like; 9 an N ⁺ type emitter region formed by implanting arsenic ions into the surface of the active base region 6 through an opening provided in the insulating film 8; 10 is an insulating film 8
^N
The collector regions 11, 12 and 13 are a base electrode, an emitter electrode and a collector electrode which are bonded to the inactive base region 7, the emitter region 9 and the N ⁺ collector region 10, respectively, through openings provided in the insulating film 8. .

This conventional bipolar transistor with an insulator isolation structure includes an N ⁺ type buried collector region 2, a P ⁺ type channel cut region 4, and an insulating isolation film 5.
to separate transistors or other elements. Therefore, compared to TTL transistors,
Base-collector junction capacitance C _TC and collector
Substrate junction capacitance _CTS is reduced to approximately 1/2 and approximately 5/6, respectively. When creating ultra-high-speed bipolar LSIs, it is important to improve the frequency characteristics of the transistor structure used. To achieve this, it is necessary to reduce the base resistance (r′ _bb ),
A structure with reduced emitter-base junction capacitance C _TE , base-collector junction capacitance C _TC , collector-substrate junction capacitance C _TS , narrow base width, and low collector resistance must be realized with good reproducibility. The advantages of transistor miniaturization are the above-mentioned _CTE ,
We expect the effect of reducing C _TC and C _TS . For example, in a transistor with a fine emitter structure of 3 × 4 μm ² , C _TE = 0.05 pF, C _TC =
It has a small capacitance of 0.04 pF, C _TS =0.16 pF, a cutoff frequency f _T =2 MHz, and an LSI using this transistor has a propagation delay speed of 0.05 ns/gate.

However, in the conventional transistor structure,
Unless the buried collector region 2 extends not only to the active region of the transistor (that is, the part directly below the emitter) but also to the bottom of the inactive base region ₇ , isolation between elements cannot be achieved. As you can see, it accounts for 64% of the junction capacity.
When trying to speed up bipolar LSI,
With conventional structures, even if miniaturization progressed, the collector-substrate junction capacitance _CTS could not be made sufficiently small, so there was a limit to speed increases.

The present invention was made in order to eliminate the drawbacks of the conventional structure as described above, and by providing a buried collector region only directly under the active region of the transistor, the collector-substrate junction capacitance _CTS , which has the largest ratio among transistor junction capacitances, can be reduced. The present invention aims to provide a bipolar semiconductor device for ultra-high-speed logic LSI that has a significantly higher cutoff frequency by significantly reducing the base-collector junction capacitance _CTC .

Hereinafter, the present invention will be explained based on Examples.

FIG. 2 is a longitudinal cross-sectional view of a main part of an embodiment of a semiconductor device according to the present invention. In FIG. 2, the same reference numerals as in FIG. 1 represent the same components as shown in FIG. 2a is an N ⁺ type buried collector region formed only directly under the active region of the transistor, and 4a is a P ⁺ type channel cut region formed in a portion of the upper surface of the semiconductor substrate 1 where the buried collector region 2a is not formed. , 14 is a first oxide film formed on the channel cut region 4a and used for forming the buried collector region 2a;
3a is an epitaxial layer formed on the buried collector region 2a and on the first oxide film 14. A portion of the epitaxial layer 3a above the buried collector region 2a becomes a single crystal region, and a portion above the first oxide film 14 becomes a polycrystalline region. 7a and 1
5 is a P ⁺ type inactive base region whose main portion is formed in the polycrystalline region of the epitaxial layer 3a and an N ⁺
A shaped leading collector region 16 is a second oxide film formed on the epitaxial layer 3a including the active base region 6, the inactive base region 7a and the leading collector region 15 formed therein. .
The second oxide film 16 is integrated with the first oxide film at the portion where it is in contact with the first oxide film.

Next, a manufacturing method for manufacturing the semiconductor device of the embodiment shown in FIG. 2 will be explained with reference to longitudinal sectional views of main manufacturing steps shown in FIGS. 3a to 3j. First, as shown in FIG. 3a, boron ions are implanted into the entire surface of the semiconductor substrate 1 made of P-type silicon.
P ⁺ to form the channel cut region 4a in a later process
A shape layer 4x is formed. Next, as shown in FIG. 3b, the surface of the P ⁺ type layer 4x is oxidized to form a first oxide film 14. Next, as shown in Figure 3c,
An opening is provided in the first oxide film 14, and arsenic ions are implanted into the semiconductor substrate 1 through the opening to form an N ⁺ layer 2x which will become the buried collector region 2a in a later step. At this time, the P ⁺ type layer 4x becomes the channel cut region 4a. Next, as shown in FIG. 3d, an epitaxial layer 3a is formed entirely on the N ⁺ type layer 2x and the first oxide film 14. At this time, the epitaxial layer 3a on the first oxide film 14
becomes polycrystalline, and the epitaxial layer 3a on the exposed surface of the N ⁺ type layer 2x becomes single crystal. Also, N ⁺
A portion of the shaped layer 2x floats up into the epitaxial layer 3a, thereby becoming a buried collector region 2a. Next, as shown in FIG. 3e, the portion of the epitaxial layer 3a other than the portion where the lead-out collector region 15 is formed is covered with a resist film 17, and arsenic is ion-implanted as shown by the arrow in the figure to form an N ⁺ type polycrystal. Area 15
form x. By removing the resist film 17 and annealing, the N ⁺ type polycrystalline region 15 is formed.
The impurity x is diffused into the extraction collector region 15.
is formed and connected to the buried collector region 2a.
At this time, since the diffusion coefficient in the polycrystal is several times the diffusion coefficient in the single crystal, the resistance value of the polycrystalline region becomes extremely small. Moreover, in the direction of the single crystal region,
Since it is diffused relatively uniformly in the lateral direction, the lead-out collector region 15 and the buried collector region 2a can be connected while the buried collector region 2a is less lifted up. First oxide film 14
serves to prevent arsenic in the polycrystalline region from further diffusing into the semiconductor substrate 1. Next, as shown in FIG. 3f, the epitaxial layer 3a in the regions that will become the collector, emitter and base, that is, the region that will become the transistor, is covered with a resist film 18, and the regions that are not covered with the resist film 18 in the polycrystalline region are covered with a resist film 18. The portion is removed by dry etching such as plasma etching. At this time, the first oxide film 14 is
It acts as a protective film and protects the semiconductor substrate 1 from etching. Next, as shown in FIG. 3g, the region that will become the collector of the epitaxial layer 3a is covered with a resist film 19, and boron ions are implanted into the region that will become the base as shown by the arrow in the figure to form the P-type layer 6x. Form. Next, as shown in FIG. 3h, the portions of the epitaxial layer 3a that will become the lead-out collector region 15 and the active base region 6 are covered with a resist film 20, and the portions that will become the inactive base region 7a are coated as shown by the arrows in the figure. Boron is implanted at a high concentration to form a P ⁺ type polycrystalline region 7ax. Next, as shown in FIG. 3i, the resist film 20 is removed and annealing is performed to form the active base region 6 and the inactive base region 7a, and the polycrystalline region and single crystal region of the epitaxial layer 3a are removed. A second oxide film 16 is formed over the region and the exposed surface of the first oxide film 14 . At this time, since the inactive base region 7a is formed in a polycrystalline region, impurities are quickly diffused and
It reaches the first oxide film 14 and is then diffused laterally. That is, all polycrystalline regions have a uniformly high boron concentration. Next, as shown in FIG. 3j, emitters and
Openings for the base and collector are formed, the base opening is covered with a resist film 21, arsenic ions are implanted as shown by the arrows through the emitter and collector openings, and then the resist film 21 is removed and annealing is performed. . At this time, emitter region 9 is formed. Next, the emitter electrode 12, the base electrode 11, and the collector electrode 13 are bonded to the emitter region 9, the inactive base region 7a, and the lead-out collector region 15 through the openings for the emitter, base, and collector, respectively. The main parts of the example device are completed. Note that as the electrode structure, a three-layer structure consisting of platinum, silicon, titanium, tungsten, and aluminum, a three-layer structure consisting of platinum/silicon, titanium/tungsten, and gold, etc. are used. In addition, by using a large number of the above transistors and using multilayer wiring,
It is possible to manufacture LSIs for high-speed logic operation circuits.

As described above, in the semiconductor device according to the present invention, only the active region of the transistor is formed in a single crystal, and the region outside the depletion layer is entirely polycrystalline, so all PN junctions of the transistor are formed in a single crystal region. has been done. Therefore, although leakage current is a problem in a PN junction in a polycrystalline region, the semiconductor structure according to the present invention does not have any adverse effect on the electrical characteristics of the junction. In increasing the speed of LSI, the cutoff frequency f _T of the element transistor is
It is important to widen the operating range of the transistor at high frequencies by increasing the To this end, it is important to reduce parameters that contribute to charging and discharging, that is, collector resistance r _C , collector-substrate junction capacitance C _TS , and base-collector junction capacitance C _TC . Since it is made of polycrystalline silicon and has a high concentration distribution structure that is graded in the vertical direction, r _C is extremely small, approximately half that of the conventional structure. Furthermore, the area of the buried collector region 2a is reduced to about ⅓ compared to the conventional structure. In addition, the area of the collector-base junction is approximately 1/2 that of the conventional structure. Therefore, C _TS , C _TC
are 1/3 and 1/2 respectively. In order to increase f _T , it is sufficient to decrease r _C (C _TS + C _TC ), but r _C
Since (C _TS + C _TC ) can be reduced to about 5/12 of the conventional structure, the gate delay time as an LSI is significantly smaller than that of the conventional structure. r _C (C _TS + C _TC )
When t pd decreases by 30%, the propagation delay speed t _pd decreases by about 10%. In the structure of the example, r _C (C _TS + C _TC ) is improved by 60% compared to the conventional emitter structure, so t _pd is reduced by about 20%, making it possible to create an extremely high-performance device as an ultra-high-speed logic device. can get.

Furthermore, according to the present invention, isolation between elements is extremely simple. In the conventional structure, the thickness of the epitaxial layer 3, the thickness of the insulating isolation film 5, and the etching depth of the epitaxial layer 3 mutually affect the isolation breakdown voltage, and it was necessary to control these with precision. According to the invention, even if the thickness of the epitaxial layer 3a, the etching depth of the epitaxial layer 3a, etc. are completely independent parameters, there is an advantage that element isolation can be obtained independently. This is extremely important in manufacturing, as it is inexpensive and has a high yield.
This structure is also significantly advantageous compared to the conventional structure in terms of obtaining elements.

Furthermore, the third advantage of the present invention is that it can be manufactured by an extremely simple process compared to the isolation structure using a selective oxide film in the conventional structure. That is, in the conventional structure, defects occur in the epitaxial layer 3 in the active region at the boundary between the epitaxial layer 3 and the insulating isolation film 5 due to internal strain caused by the thick oxide film and nitride film used for etching the epitaxial layer 3. When tens of thousands of devices are formed as an LSI, defects that occur in some of them tend to cause the emitter pipe phenomenon and an increase in leakage current due to the base-collector junction characteristics, which reduces manufacturing yield. It was also necessary to consider each process from this point of view. In the structure according to the present invention, only the active region, that is, the region where the depletion layer occurs, has a single crystal structure, and crystal defects occur only in the region where the depletion layer does not spread, so the electrical characteristics of the device are extremely stable. becomes.

In addition, in the present invention, the epitaxial layer 3a is etched mainly in the polycrystalline region, and the first oxide film 14 is placed therebeneath. The difference in etching depth, which used to be about 12% between the center of the wafer and the periphery of the wafer, can now be reduced to about 1 throughout the entire wafer, making it easy to estimate the difference in level during design.

In addition, in the conventional structure, the breakdown voltage of the element (BV _CEO ,
BV _CBO ) is controlled by the etching of the epitaxial layer 3 and the thickness of the insulating separation film 5 to the extent that crystal defects do not occur. Autodoping from the collector region 2 limits the thickness of the remaining epitaxial layer, and only a finite narrow range of values can be designed. That is,
BV _CEO = 5 to 12V, BV _CBO = about 20 to 30V. This poses no problem when LSI is used as a digital logic element, but when an oxide film isolation structure is applied as a bipolar high-speed linear element, it becomes a barrier in terms of breakdown voltage.

However, in the structure according to the present invention, no matter how thick the epitaxial layer 3a is, the isolation breakdown voltage can be obtained independently, and the occurrence of crystal defects does not affect the device, so that a device with the desired breakdown voltage can be obtained. Therefore, the scope of application of the oxide film isolation structure can be expanded to an extremely wide area. In terms of the degree of integration, the conventional structure attempts to integrate the floating collector of one element to the extent that the floating collector of another element does not collide, but in the structure according to the present invention, as mentioned above, the integration of the elements is Since isolation is achieved only in the vicinity directly below the active region, the degree of integration of the device is determined by the spacing between the metal wirings.
While the conventional element spacing is 12 μm in 4K ECLRAM, the structure according to the present invention can be reduced to 3 μm, resulting in an approximately 20% improvement in the degree of integration.

In the above embodiment, the silicon island portion is formed higher than the substrate, so when used as an LSI and for high breakdown voltage, the epitaxial layer 3a is made thicker, so that the metal wiring is likely to break. Therefore, as shown in the vertical cross-sectional view of FIG. 4, by slightly etching the epitaxial layer 3a over the entire surface in the step of FIG. 3d, a low level difference can be achieved. Furthermore, as shown in the longitudinal cross-sectional view of FIG. 5, by etching the surface of the polycrystalline region of the epitaxial layer 3a twice in the step of FIG. 3f, a structure with fewer steps can be obtained. It is possible.

In addition, the P-type region in the above embodiment is changed to N-type, and N
It goes without saying that the present invention is also applicable to a semiconductor device in which the shaped region is P-shaped.

According to the structure according to the present invention, not only is ultra-high-speed LSI possible as described above, but also sufficient separation can be achieved no matter how thick the epitaxial layer is, so that it can be used from low to high withstand voltages. Element design is possible, and the degree of integration is improved because separation is easier than in the past, allowing elements to be brought closer to the spacing allowed by metal wiring.

[Brief explanation of drawings]

FIG. 1 is a vertical sectional view of a main part of an example of a conventional semiconductor device, FIG. 2 is a vertical sectional view of a main part of an embodiment of a semiconductor device according to the present invention, and FIG. 3 is an embodiment shown in FIG. 4 and 5 are longitudinal sectional views of main parts of other embodiments of the semiconductor device according to the present invention, respectively. In the figure, 1 is a semiconductor substrate, 2a is a buried collector region, 3a is an epitaxially grown semiconductor layer, 4a is a channel cut region, 6 is an active base region, 9 is an emitter region, 11 is a base electrode, 1
2 is an emitter electrode, 13 is a collector electrode, 14 is a first oxide film (first insulating film), 15 is a collector region for extraction, and 16 is a second oxide film (second insulating film). Note that the same reference numerals in the figures indicate the same or corresponding parts.

Claims (1)

[Scope of Claims] 1. A semiconductor substrate of a first conductivity type, a first insulating film formed on one main surface of this semiconductor substrate and having an opening for forming a buried collector region, and an epitaxially grown semiconductor layer formed on a portion surrounding the opening of the first insulating film and having a polycrystalline region above the first insulating film and a single crystalline region elsewhere; the semiconductor substrate and the epitaxially grown semiconductor layer; a buried collector region having a second conductivity type and having a high impurity concentration;
a channel cut region having a conductivity type of and having a high impurity concentration; an active base region of a first conductivity type formed in a surface portion of the single crystal region of the epitaxially grown semiconductor layer; From the surface to the main half of the crystal region, the first
an inactive base region having a first conductivity type and having a high impurity concentration, a main portion of which is formed so as to reach the insulating film of the epitaxially grown semiconductor layer; A main part is formed in the polycrystalline region and is connected to the buried collector region over a wide area by diffusion of impurities from the polycrystalline region to the single crystal region, and has a second conductivity type and has a high impurity concentration. a collector region of a second conductivity type consisting of a portion other than the active base region, the inactive base region and the lead-out collector region of the grown semiconductor layer; a collector region of a second conductivity type formed on a surface portion of the active region; an emitter region, a second insulating film continuously formed on the first insulating film and the epitaxially grown semiconductor layer, and an opening formed in the second insulating film to form an inactive emitter region, respectively. A semiconductor device comprising an emitter electrode, a base electrode, and a collector electrode bonded to a base region and a collector region for extraction. 2. The semiconductor device according to claim 1, wherein the thickness of the main portion of the polycrystalline region of the epitaxially grown semiconductor layer is thinner than the thickness of the main portion of the single crystal region. 3. The semiconductor device according to claim 1 or 2, characterized in that the thickness of the polycrystalline region of the epitaxially grown semiconductor layer is gradually thinned as the distance from the single crystal region increases.