JPS6346830U - - Google Patents

Info

Publication number
JPS6346830U
JPS6346830U JP14153286U JP14153286U JPS6346830U JP S6346830 U JPS6346830 U JP S6346830U JP 14153286 U JP14153286 U JP 14153286U JP 14153286 U JP14153286 U JP 14153286U JP S6346830 U JPS6346830 U JP S6346830U
Authority
JP
Japan
Prior art keywords
inductance
multilayer
filter according
chip filter
multilayer chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14153286U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP14153286U priority Critical patent/JPS6346830U/ja
Publication of JPS6346830U publication Critical patent/JPS6346830U/ja
Pending legal-status Critical Current

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Landscapes

  • Coils Or Transformers For Communication (AREA)
  • Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
  • Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
  • Filters And Equalizers (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案における積層セラミツクコンデ
ンサを構成するセラミツクシートの平面図、第2
図は第1図のセラミツクシートを積層焼結して成
る積層セラミツクコンデンサの斜視図、第3図は
第2図の積層セラミツクコンデンサにチツプイン
ダクタンスを組合わせて形成した本考案の積層チ
ツプフイルタの一実施例を示す側面図、第4図は
第3図の積層チツプフイルタの等価回路図、第5
図乃至第7図はそれぞれ本考案の他の実施例を示
す側面図、第8図は外装を施した実施例を示す斜
視図、第9図は個別部品によるフイルタと本考案
の積層チツプフイルタとの特性を比較したグラフ
である。 S……セラミツクシート、C……積層セラミツ
クコンデンサ、1,1′……独立電極、2……共
通電極、3……チツプインダクタンス、4……端
子、5……リード線、6……フエライトビーズ、
7……コイル、8……リード線、9……外装。
Figure 1 is a plan view of a ceramic sheet constituting the multilayer ceramic capacitor of the present invention;
The figure is a perspective view of a multilayer ceramic capacitor made by laminating and sintering the ceramic sheets shown in Fig. 1, and Fig. 3 is an embodiment of the multilayer chip filter of the present invention formed by combining the multilayer ceramic capacitor shown in Fig. 2 with a chip inductance. A side view showing an example, FIG. 4 is an equivalent circuit diagram of the multilayer chip filter in FIG. 3, and FIG.
7 to 7 are side views showing other embodiments of the present invention, FIG. 8 is a perspective view showing an embodiment with an exterior, and FIG. 9 is a combination of a filter made of individual parts and a laminated chip filter of the present invention. This is a graph comparing characteristics. S...ceramic sheet, C...multilayer ceramic capacitor, 1, 1'...independent electrode, 2...common electrode, 3...chip inductance, 4...terminal, 5...lead wire, 6...ferrite bead ,
7...Coil, 8...Lead wire, 9...Exterior.

Claims (1)

【実用新案登録請求の範囲】 (1) 誘電体を原料とする四辺形のセラミツクシ
ートの一面に独立した2つの電極を形成し、それ
ぞれの電極は四辺形の相対する2辺より独立して
外部に導出し、 このセラミツクシートの他面には前記2つの独
立電極のそれぞれに対して共通に相対する共通電
極を形成し、この共通電極を前記独立電極が外部
に導出されている2辺以外の辺より外部に導出し
、 上記のようにして両面に電極を設けたセラミツ
クシートを同一方向に複数枚積層焼結し、 同一位置の電極同士を外部側面にて共通接続し
て積層セラミツクコンデンサが形成され、 この積層セラミツクコンデンサの2つの独立電
極間にインダクタンスを接続したことを特徴とす
る積層チツプフイルタ。 (2) 2つの独立電極が、積層セラミツクコンデ
ンサの側面から上面に掛けて延長形成されている
実用新案登録請求の範囲第1項記載積層チツプフ
イルタ。 (3) インダクタンスが、チツプインダクタンス
である実用新案登録請求の範囲第1項記載の積層
チツプフイルタ。 (4) インダクタンスが、リード線である実用新
案登録請求の範囲第1項記載の積層チツプフイル
タ。 (5) インダクタンスが、フエライトビーズの穴
を貫通したリード線である実用新案登録請求の範
囲第1項記載の積層チツプフイルタ。 (6) インダクタンスが、コイルである実用新案
登録請求の範囲第1項記載の積層チツプフイルタ
。 (7) 積層セラミツクコンデンサ及びインダクタ
ンスが、樹脂塗料などで外装を施されたものであ
る実用新案登録請求の範囲第1項記載の積層チツ
プフイルタ。 (8) 各電極が、リード線を接続したものである
実用新案登録請求の範囲第1項記載の積層チツプ
フイルタ。
[Claims for Utility Model Registration] (1) Two independent electrodes are formed on one side of a quadrilateral ceramic sheet made from a dielectric material, and each electrode is independently connected to the outside from two opposing sides of the quadrilateral. A common electrode is formed on the other side of the ceramic sheet to commonly face each of the two independent electrodes. A multilayer ceramic capacitor is formed by sintering multiple ceramic sheets with electrodes on both sides in the same direction, leading them out from the sides, and connecting the electrodes at the same position in common on the external side. A multilayer chip filter characterized in that an inductance is connected between two independent electrodes of the multilayer ceramic capacitor. (2) The multilayer chip filter according to claim 1, wherein two independent electrodes extend from the side surface to the top surface of the multilayer ceramic capacitor. (3) The multilayer chip filter according to claim 1, wherein the inductance is a chip inductance. (4) The multilayer chip filter according to claim 1, wherein the inductance is a lead wire. (5) The multilayer chip filter according to claim 1, wherein the inductance is a lead wire passing through a hole in a ferrite bead. (6) The multilayer chip filter according to claim 1, wherein the inductance is a coil. (7) The multilayer chip filter according to claim 1, wherein the multilayer ceramic capacitor and inductance are coated with resin paint or the like. (8) The laminated chip filter according to claim 1, wherein each electrode is connected to a lead wire.
JP14153286U 1986-09-16 1986-09-16 Pending JPS6346830U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14153286U JPS6346830U (en) 1986-09-16 1986-09-16

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14153286U JPS6346830U (en) 1986-09-16 1986-09-16

Publications (1)

Publication Number Publication Date
JPS6346830U true JPS6346830U (en) 1988-03-30

Family

ID=31049403

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14153286U Pending JPS6346830U (en) 1986-09-16 1986-09-16

Country Status (1)

Country Link
JP (1) JPS6346830U (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS545755B2 (en) * 1975-10-07 1979-03-20

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS545755B2 (en) * 1975-10-07 1979-03-20

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