JPS6347143B2 - - Google Patents

Info

Publication number
JPS6347143B2
JPS6347143B2 JP56091799A JP9179981A JPS6347143B2 JP S6347143 B2 JPS6347143 B2 JP S6347143B2 JP 56091799 A JP56091799 A JP 56091799A JP 9179981 A JP9179981 A JP 9179981A JP S6347143 B2 JPS6347143 B2 JP S6347143B2
Authority
JP
Japan
Prior art keywords
semiconductor
chips
chip
common
individual
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP56091799A
Other languages
English (en)
Other versions
JPS57207356A (en
Inventor
Yoshihiro Takemae
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP56091799A priority Critical patent/JPS57207356A/ja
Priority to EP82303014A priority patent/EP0067677B1/en
Priority to DE8282303014T priority patent/DE3277268D1/de
Priority to US06/388,616 priority patent/US4578697A/en
Publication of JPS57207356A publication Critical patent/JPS57207356A/ja
Publication of JPS6347143B2 publication Critical patent/JPS6347143B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/611—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W76/00—Containers; Fillings or auxiliary members therefor; Seals
    • H10W76/10—Containers or parts thereof
    • H10W76/12—Containers or parts thereof characterised by their shape
    • H10W76/15—Containers comprising an insulating or insulated base
    • H10W76/157—Containers comprising an insulating or insulated base having interconnections parallel to the insulating or insulated base
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/682—Shapes or dispositions thereof comprising holes having chips therein
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H10W72/07351—Connecting or disconnecting of die-attach connectors characterised by changes in properties of the die-attach connectors during connecting
    • H10W72/07353—Connecting or disconnecting of die-attach connectors characterised by changes in properties of the die-attach connectors during connecting changes in shapes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H10W72/331—Shapes of die-attach connectors
    • H10W72/334—Cross-sectional shape, i.e. in side view
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/5445—Dispositions of bond wires being orthogonal to a side surface of the chip, e.g. parallel arrangements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/551—Materials of bond wires
    • H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
    • H10W72/5522—Materials of bond wires comprising metals or metalloids, e.g. silver comprising gold [Au]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/551—Materials of bond wires
    • H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
    • H10W72/5524—Materials of bond wires comprising metals or metalloids, e.g. silver comprising aluminium [Al]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/59—Bond pads specially adapted therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/884—Die-attach connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/931—Shapes of bond pads
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/931—Shapes of bond pads
    • H10W72/932—Plan-view shape, i.e. in top view
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W76/00—Containers; Fillings or auxiliary members therefor; Seals
    • H10W76/10—Containers or parts thereof
    • H10W76/17—Containers or parts thereof characterised by their materials
    • H10W76/18—Insulating materials, e.g. resins, glasses or ceramics
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Wire Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Description

【発明の詳細な説明】 本発明は半導体装置の構造に係り、特に一つの
パツケージに複数個の半導体チツプが搭載される
構造の半導体装置の構造に関する。
半導体記憶装置、半導体論理装置等の半導体集
積回路（IC）装置に於ては、従来から一般に一
つのパツケージ内に１〔個〕の半導体ICチツプが
搭載された構造が用いられているが、コンピユー
タ等の電子装置が高性能化並びに大容量化される
に伴つて、それに比例してこれら電子装置に対す
る半導体パツケージの搭載数が増大し、電子装置
が大型化するという問題があつた。そこで半導体
IC素子の実装密度を上げて電子装置の大型化を
防止する手段として、一つのパツケージ内に従来
構造のICチツプを複数個搭載してパツケージ当
りの記憶容量やゲート数を増大したチツプ・アレ
イ構造の半導体IC装置もしばしば用いられるが、
このような従来のチツプ・アレイ構造半導体IC
に於てはパツケージ内に於けるボンデイング・ワ
イヤの交差を避けるために、多層セラミツク配線
基板を用いて形成した半導体パツケージを用いる
必要があつた。従つてパツケージが高価になり半
導体IC装置の原価が大幅に上昇するという問題
があつた。
本発明は上記問題点に鑑み、半導体チツプ及び
半導体パツケージの構造を改良し、低原価で製造
することが可能なチツプ・アレー方式の半導体装
置を提供する。
即ち本発明は、一つのパツケージに複数個の半
導体チツプが搭載される構造の半導体装置に於
て、Ｘ方向側縁部に沿つて共通配線パツドが配設
されてなる半導体チツプが、Ｘ方向に沿つて帯状
に形成された共通配線を有してなる半導体パツケ
ージに搭載され、前記半導体チツプの共通配線パ
ツドが、前記半導体パツケージの共通配線に接続
されてなることを等徴とする。
以下本発明を実施例について第１図乃至第４図
に用いて詳細に説明する。なお第１図は本発明の
一実施例に於ける半導体ICチツプの上面図、第
２図は同一実施例に於ける半導体パツケージの上
面図ａ、Ａ―A′矢視断面図ｂ及びＢ―B′矢視断
面図ｃ、第３図は同実施例に於ける組立完成体の
上面図ａ、Ａ―A′矢視断面図ｂ及びＢ―B′矢視
断面図ｃ、第４図は同実施例に於ける封止完成体
のＸ方向断面図ａ及びＹ方向断面図ｂである。
本発明の構造を有する半導体IC装置に搭載さ
れる半導体ICチツプに於ては、例えば第１図に
示すように、各ICチツプに共通な電源（Vss，
Vcc等）及び信号（アドレス信号等）供給用の共
通配線パツド１ａ，１ｂ，１ｃ，１ｄ，１ｅ，１
ｆがICチツプ２の例えばＸ方向に面する縁部に
沿つて形成され、又チツプ毎に異なる信号（クロ
ツク信号、入出力信号等）用の個別配線パツド３
が、ICチツプ２の例えばＹ方向に面する縁部に
沿つて形成される。なおここで個別配線パツド
は、必ずしもチツプ２のＹ方向に面する縁部に沿
つて配設される必要はなく、チツプ上にランダム
に形成されても良い。又各配線パツドは通常通り
アルミニウム（Al）等により形成される。
又本発明の半導体装置には単層配線方式の半導
体パツケージが用いられその構造は、例えば第２
図ａ乃至ｃに示すように、チツプ搭載用の凹部４
を有するアルミナ等のセラミツク基板５上に、同
種の材質からなり上面に封止用メタライズ層６を
有するセラミツク枠７が、ガラス（図示せず）等
により融着されてなつている。そしてセラミツク
基板５の上面にはその凹部４を含めてパツケージ
のＸ方向（長辺側）端面に平行に、印刷法或るい
はフオト・リソグラフイによつて形成された金等
のメタライズ層からなる複数条の共通配線８ａ，
８ｂ，８ｃ，８ｄ，８ｅ，８ｆが配設されてい
る。なおこれら共通配線８ａ〜８ｆの一端部はセ
ラミツク基板５のＸ方向に沿つた（長辺側）端面
に延出されている。又該セラミツク基板５の上面
には、更にその凹部４の両側に前記共通配線８ａ
〜８ｆを挾んで対向し、その一端部がセラミツク
基板５のＸ方向に沿つた（長辺側）端面に延出さ
れた共通配線８ａ〜８ｆと同質の個別配線９が配
設されている。なおこれら配線の前記凹部４の縁
に表出している領域をボンデイング・ポスト部と
称する。そして又凹部４内にはアルミナ或るいは
ベリリア等のセラミツク板からなるチツプ台１０
がガラス（図示せず）等により融着されている。
又前記配線８ａ〜８ｆ及び９の、セラミツク基板
５端面に延出された部分には、コバール等からな
る外部リード１１がろう付けされている。
本発明の構造を有する半導体装置は例えば第３
図ａ乃至ｃに示すように、前記半導体パツケージ
１２の複数のチツプ台１０上に、それぞれ前記半
導体ICチツプ２が、エポキシ樹脂（図示せず）
等により接着搭載され、これら半導体ICチツプ
２の共通配線パツド１ａ，１ｂ，１ｃ，１ｄ，１
ｅ，１ｆと、半導体パツケージ１２の共通配線８
ａ，８ｂ，８ｃ，８ｄ，８ｅ，８ｆのボンデイン
グ・ポスト部が、アルミニウム或るいは金等から
なるボンデイング・ワイヤ１４でそれぞれ接続さ
れ、又半導体ICチツプ２の個別配線パツド３と、
半導体パツケージ１２の所望個別配線９のボンデ
イング・ポスト部が、ボンデイング・ワイヤ１
４′でそれぞれ接続されてなつている。
第４図ａ及びｂは上記半導体装置の封止完了の
状態を示したもので、図中１は共通配線パツド、
２は半導体ICチツプ、３は個別配線パツド、５
はセラミツク基板、６は封止用メタライズ層、７
はセラミツク枠、８は共通配線、９は個別配線、
１０はチツプ台、１１は外部リード、１２は半導
体パツケージ、１３はセラミツク等からなるキヤ
ツプ、１４及び１４′はボンデイング・ワイヤ、
１５はろう材を示す。
上記実施例に於ては本発明の構造に於て、共通
配線上に搭載される半導体チツプと共通配線との
間の絶縁体としてセラミツクからなるチツプ台を
用いたが、背面に厚い絶縁膜を形成させた半導体
チツプ、或るいはSOSチツプ等を用いる際には、
上記チツプ台を省略しても良い。
以上説明したように本発明に於ては、安価に製
造できる単層配線構造の半導体パツケージを用い
て、チツプ・アレイ構造の半導体装置が形成され
る。従つて本発明によれば、低原価で実装密度の
高い半導体装置が提供され、コンピユータ等の電
子装置の小型化が図れる。
【図面の簡単な説明】
第１図は本発明の一実施例に於ける半導体IC
チツプの上面図、第２図は同実施例に於ける半導
体パツケージの上面図ａ、Ａ―A′矢視断面図ｂ
及びＢ―B′矢視断面図ｃ、第３図は同実施例に
於ける組立完成体の上面図ａ、Ａ―A′矢視断面
図ｂ及びＢ―B′矢視断面図ｃ、第４図は同実施
例に於ける封止完成体のＸ方向断面図ａ及びＹ方
向断面図ｂである。 図に於て、１，１ａ，１ｂ，１ｃ，１ｄ，１
ｅ，１ｆは共通配線パツド、２は半導体ICチツ
プ、３は個別配線パツド、４は凹部、５はセラミ
ツク基板、６は封止用メタライズ層、７はセラミ
ツク枠、８，８ａ，８ｂ，８ｃ，８ｄ，８ｅ，８
ｆは共通配線、９は個別配線、１０はチツプ台、
１１は外部リード、１２は半導体パツケージ、１
３はセラミツク・キヤツプ、１４及び１４′はボ
ンデイング・ワイヤ、１５はろう材を示す。

Claims (1)

  1. 【特許請求の範囲】 １ 表面に回路素子が形成され且つ共通配線パツ
    ド及び個別配線パツドが配設された複数個の半導
    体チツプと、 該半導体チツプが搭載されるパツケージを具備
    し、該パツケージにＸ方向に延びる複数の共通配
    線と、該複数共通配線の少なくとも一方の側縁に
    位置する個別配線とが設けられ、該半導体チツプ
    が、該共通配線上に位置し、該共通配線パツドが
    該共通配線に、該個別配線パツドが該個別配線に
    それぞれ接続されてなることを特徴とする半導体
    装置。
JP56091799A 1981-06-15 1981-06-15 Semiconductor device Granted JPS57207356A (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP56091799A JPS57207356A (en) 1981-06-15 1981-06-15 Semiconductor device
EP82303014A EP0067677B1 (en) 1981-06-15 1982-06-10 Chip-array-constructed semiconductor device
DE8282303014T DE3277268D1 (en) 1981-06-15 1982-06-10 Chip-array-constructed semiconductor device
US06/388,616 US4578697A (en) 1981-06-15 1982-06-15 Semiconductor device encapsulating a multi-chip array

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56091799A JPS57207356A (en) 1981-06-15 1981-06-15 Semiconductor device

Publications (2)

Publication Number Publication Date
JPS57207356A JPS57207356A (en) 1982-12-20
JPS6347143B2 true JPS6347143B2 (ja) 1988-09-20

Family

ID=14036658

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56091799A Granted JPS57207356A (en) 1981-06-15 1981-06-15 Semiconductor device

Country Status (4)

Country Link
US (1) US4578697A (ja)
EP (1) EP0067677B1 (ja)
JP (1) JPS57207356A (ja)
DE (1) DE3277268D1 (ja)

Families Citing this family (42)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3382726D1 (de) * 1982-06-30 1994-01-27 Fujitsu Ltd Integrierte Halbleiterschaltungsanordnung.
JPS60143641A (ja) * 1983-12-29 1985-07-29 Konishiroku Photo Ind Co Ltd 集積回路装置
GB8412674D0 (en) * 1984-05-18 1984-06-27 British Telecomm Integrated circuit chip carrier
EP0334397A3 (en) * 1984-05-18 1990-04-11 BRITISH TELECOMMUNICATIONS public limited company Circuit board
GB2170657B (en) * 1985-02-05 1988-01-27 Stc Plc Semiconductor memory device
US4674007A (en) * 1985-06-07 1987-06-16 Microscience Corporation Method and apparatus for facilitating production of electronic circuit boards
FR2591801B1 (fr) * 1985-12-17 1988-10-14 Inf Milit Spatiale Aeronaut Boitier d'encapsulation d'un circuit electronique
US4751564A (en) * 1986-05-05 1988-06-14 Itt Corporation Multiple wafer scale assembly apparatus and fixture for use during the fabrication thereof
US4774635A (en) * 1986-05-27 1988-09-27 American Telephone And Telegraph Company At&T Bell Laboratories Semiconductor package with high density I/O lead connection
USRE36894E (en) * 1986-05-27 2000-10-03 Lucent Technologies Inc. Semiconductor package with high density I/O lead connection
IT1218104B (it) * 1986-06-27 1990-04-12 Sgs Microelettronica Spa Metodo di progettazione di microcalcolatori integrati e microcalcolatore integrato a struttura modulare ottenuto con il metodo suddetto
KR900007231B1 (ko) * 1986-09-16 1990-10-05 가부시키가이샤 도시바 반도체집적회로장치
US4816422A (en) * 1986-12-29 1989-03-28 General Electric Company Fabrication of large power semiconductor composite by wafer interconnection of individual devices
US4868712A (en) * 1987-02-04 1989-09-19 Woodman John K Three dimensional integrated circuit package
JPH0834264B2 (ja) * 1987-04-21 1996-03-29 住友電気工業株式会社 半導体装置およびその製造方法
US5016138A (en) * 1987-10-27 1991-05-14 Woodman John K Three dimensional integrated circuit package
US4918335A (en) * 1987-11-06 1990-04-17 Ford Aerospace Corporation Interconnection system for integrated circuit chips
US4858072A (en) * 1987-11-06 1989-08-15 Ford Aerospace & Communications Corporation Interconnection system for integrated circuit chips
JP2560805B2 (ja) * 1988-10-06 1996-12-04 三菱電機株式会社 半導体装置
US4924291A (en) * 1988-10-24 1990-05-08 Motorola Inc. Flagless semiconductor package
US5255156A (en) * 1989-02-22 1993-10-19 The Boeing Company Bonding pad interconnection on a multiple chip module having minimum channel width
SG46176A1 (en) * 1989-09-15 1998-02-20 Ibm Design system for vlsi chips arranged on a carrier and module thus designed
US5191404A (en) * 1989-12-20 1993-03-02 Digital Equipment Corporation High density memory array packaging
US5081563A (en) * 1990-04-27 1992-01-14 International Business Machines Corporation Multi-layer package incorporating a recessed cavity for a semiconductor chip
FR2680262B1 (fr) * 1991-08-08 1993-10-08 Gemplus Card International Circuits integres pour carte a puce et carte a plusieurs puces utilisant ces circuits.
US5212406A (en) * 1992-01-06 1993-05-18 Eastman Kodak Company High density packaging of solid state devices
US5340772A (en) * 1992-07-17 1994-08-23 Lsi Logic Corporation Method of increasing the layout efficiency of dies on a wafer and increasing the ratio of I/O area to active area per die
DE4225154A1 (de) * 1992-07-30 1994-02-03 Meyerhoff Dieter Chip-Modul
US5325268A (en) * 1993-01-28 1994-06-28 National Semiconductor Corporation Interconnector for a multi-chip module or package
JPH07161919A (ja) * 1993-12-03 1995-06-23 Seiko Instr Inc 半導体装置およびその製造方法
JP3269745B2 (ja) 1995-01-17 2002-04-02 株式会社日立製作所 モジュール型半導体装置
US6064116A (en) * 1997-06-06 2000-05-16 Micron Technology, Inc. Device for electrically or thermally coupling to the backsides of integrated circuit dice in chip-on-board applications
US6201186B1 (en) 1998-06-29 2001-03-13 Motorola, Inc. Electronic component assembly and method of making the same
US6418490B1 (en) * 1998-12-30 2002-07-09 International Business Machines Corporation Electronic circuit interconnection system using a virtual mirror cross over package
GB9915076D0 (en) * 1999-06-28 1999-08-25 Shen Ming Tung Integrated circuit packaging structure
WO2011017676A1 (en) 2009-08-07 2011-02-10 Advanced Processor Architectures, Llc Distributed computing
US9429983B1 (en) 2013-09-12 2016-08-30 Advanced Processor Architectures, Llc System clock distribution in a distributed computing environment
US11042211B2 (en) 2009-08-07 2021-06-22 Advanced Processor Architectures, Llc Serially connected computing nodes in a distributed computing system
US9645603B1 (en) 2013-09-12 2017-05-09 Advanced Processor Architectures, Llc System clock distribution in a distributed computing environment
US9420715B2 (en) * 2012-06-07 2016-08-16 Intal Tech Ltd. Electrononic equipment building blocks for rack mounting
JP6314591B2 (ja) * 2014-03-27 2018-04-25 三菱電機株式会社 半導体装置および半導体装置の製造方法
TWM577186U (zh) * 2018-12-11 2019-04-21 品威電子國際股份有限公司 Adapter for flexible cable

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3312771A (en) * 1964-08-07 1967-04-04 Nat Beryllia Corp Microelectronic package
US3483038A (en) * 1967-01-05 1969-12-09 Rca Corp Integrated array of thin-film photovoltaic cells and method of making same
US3568012A (en) * 1968-11-05 1971-03-02 Westinghouse Electric Corp A microminiature circuit device employing a low thermal expansion binder
US3611317A (en) * 1970-02-02 1971-10-05 Bell Telephone Labor Inc Nested chip arrangement for integrated circuit memories
US3641401A (en) * 1971-03-10 1972-02-08 American Lava Corp Leadless ceramic package for integrated circuits
US3777221A (en) * 1972-12-18 1973-12-04 Ibm Multi-layer circuit package
JPS49131863U (ja) * 1973-03-10 1974-11-13
DE2415047B2 (de) * 1974-03-28 1978-02-02 Siemens AG, 1000 Berlin und 8000 München Multichip-verdrahtung mit anschlussflaechenkonfigurationen zur kontaktierung von vier gleichen halbleiterspeicher-chips
US4038488A (en) * 1975-05-12 1977-07-26 Cambridge Memories, Inc. Multilayer ceramic multi-chip, dual in-line packaging assembly
JPS548976A (en) * 1977-06-22 1979-01-23 Nec Corp Lsi package
JPS5835367B2 (ja) * 1978-07-18 1983-08-02 ミツミ電機株式会社 回路素子基板及びその製造方法
US4297719A (en) * 1979-08-10 1981-10-27 Rca Corporation Electrically programmable control gate injected floating gate solid state memory transistor and method of making same
GB2056772B (en) * 1980-08-12 1983-09-01 Amdahl Corp Integrated circuit package and module

Also Published As

Publication number Publication date
EP0067677A2 (en) 1982-12-22
US4578697A (en) 1986-03-25
EP0067677A3 (en) 1984-10-03
DE3277268D1 (en) 1987-10-15
JPS57207356A (en) 1982-12-20
EP0067677B1 (en) 1987-09-09

Similar Documents

Publication Publication Date Title
JPS6347143B2 (ja)
JP2537014B2 (ja) 電子素子用リ―ドフレ―ム・パッケ―ジ
US5646831A (en) Electrically enhanced power quad flat pack arrangement
US5563443A (en) Packaged semiconductor device utilizing leadframe attached on a semiconductor chip
KR970006529B1 (ko) 반도체 장치
EP0538003B1 (en) Method of manufacturing inversion type ICs and IC module using same
US6815746B2 (en) Semiconductor device and method of manufacturing the same
JPH0642525B2 (ja) 多チツプチツプキヤリア及び製造方法
US6121681A (en) Semiconductor device
JP3415509B2 (ja) 半導体装置
KR100381979B1 (ko) 반도체 장치 및 그 제조방법
US4646126A (en) Semiconductor device
JPH01235264A (ja) 半導体集積回路装置
JPS59107551A (ja) 半導体装置
JPH04144269A (ja) 混成集積回路装置
JPS589585B2 (ja) デンシブヒンヨウリ−ドフレ−ム
JP3016049B2 (ja) 半導体装置
JPH07235633A (ja) マルチチップモジュール
JPH04267547A (ja) ヒートシンク付半導体パッケージ
KR200225040Y1 (ko) 적층형 반도체 패키지
JP3036976B2 (ja) マルチチップモジュール
JPH03201545A (ja) 半導体装置
JPH06125037A (ja) 半導体装置
JPS61112369A (ja) 半導体装置
JPH04287356A (ja) 半導体集積回路装置